MPC8255AZUPIBB
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 480-LBGA Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | 0°C~105°C TA |
| Packaging | Tray |
| Published | 1997 |
| Series | MPC82xx |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 480 |
| ECCN Code | 3A991.A.2 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 2V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | PC8255 |
| JESD-30 Code | S-PBGA-B480 |
| Supply Voltage-Max (Vsup) | 2.2V |
| Supply Voltage-Min (Vsup) | 1.9V |
| Speed | 300MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC G2 |
| Clock Frequency | 66.66MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | NO |
| External Data Bus Width | 64 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 3.3V |
| Ethernet | 10/100Mbps (3) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DRAM, SDRAM |
| Additional Interfaces | I2C, SCC, SMC, SPI, UART, USART |
| Co-Processors/DSP | Communications; RISC CPM |
| Height Seated (Max) | 1.65mm |
| Length | 37.5mm |
| RoHS Status | Non-RoHS Compliant |
MPC8255AZUPIBB Description
The MPC8255AZUPIBB processor delivers excellent integration of processing power for networking and communications peripherals, providing customers with an innovative, total system solution for building high-end communications systems. NXP? Semiconductors's PowerQUICC II MPC8255AZUPIBB is the next generation of the leading PowerQUICC? line of integrated communications processors, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.
MPC8255AZUPIBB Features
Dual-issue integer core
Separate power supply for internal logic and for I/O
64-bit data and 32-bit address 60x bus
32-bit data and 18-bit address local bus
The system interface unit (SIU)
Twelve-bank memory controller
A CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
MPC8255AZUPIBB Applications
Automotive
Body electronics & lighting
Industrial
Test & Measurement
Personal electronics
Gaming
