MPC8260ACZUMHBB
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 480-LBGA Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | -40°C~105°C TA |
| Packaging | Tray |
| Published | 1994 |
| Series | MPC82xx |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 480 |
| ECCN Code | 3A991.A.2 |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 2V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | PC8260 |
| JESD-30 Code | S-PBGA-B480 |
| Supply Voltage-Max (Vsup) | 2.2V |
| Supply Voltage-Min (Vsup) | 1.9V |
| Speed | 266MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC G2 |
| Clock Frequency | 66.66MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | NO |
| External Data Bus Width | 64 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 3.3V |
| Ethernet | 10/100Mbps (3) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DRAM, SDRAM |
| Additional Interfaces | I2C, SCC, SMC, SPI, UART, USART |
| Co-Processors/DSP | Communications; RISC CPM |
| Height Seated (Max) | 1.65mm |
| Length | 37.5mm |
| RoHS Status | Non-RoHS Compliant |
MPC8260ACZUMHBB Description
The MPC8260ACZUMHBB PowerQUICC? II? is an advanced integrated communications processor designed for the telecommunications and networking markets. The MPC8260ACZUMHBB now offers floating point support. The MPC8260ACZUMHBB PowerQUICC II can best be described as the next generation MPC860 PowerQUICC?, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.
Like the MPC860, the MPC8260 integrates two main components, the embedded G2 core and the Communications Processor Module (CPM). This dual-processor architecture consumes less power than traditional architectures because the CPM offloads peripheral tasks from the embedded G2 core. The CPM simultaneously supports three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), two serial management controllers (SMCs), one serial peripheral interface (SPI), and one I2C interface. The combination of the G2 core and the CPM, along with the versatility and performance of the MPC8260, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages.
MPC8260ACZUMHBB Features
190 MIPS at 100 MHz (Dhrystone 2.1)
505 MIPS at 266 MHz (Dhrystone 2.1)
570 MIPS at 300 MHz (Dhrystone 2.1)
High-performance, superscalar microprocessor
Disable CPU mode
Supports the NXP? external L2 cache chip (MPC2605)
Improved low-power core
16 Kbyte data and 16 Kbyte instruction cache, four-way set associative
Memory Management Unit
Floating point unit enabled
Common on-chip processor (COP)
MPC8260ACZUMHBB Applications
Communications equipment
Broadband fixed line access
Industrial
Appliances
Personal electronics
PC & notebooks
