MPC8270CZUUPEA
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 480-LBGA Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | -40°C~105°C TA |
| Packaging | Tray |
| Published | 1997 |
| Series | MPC82xx |
| JESD-609 Code | e0 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 4 (72 Hours) |
| Number of Terminations | 480 |
| ECCN Code | 3A991.A.2 |
| Terminal Finish | Tin/Lead/Silver (Sn/Pb/Ag) |
| HTS Code | 8542.31.00.01 |
| Subcategory | Other uPs/uCs/Peripheral ICs |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.5V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | MPC8270 |
| JESD-30 Code | S-PBGA-B480 |
| Supply Voltage-Max (Vsup) | 1.6V |
| Power Supplies | 1.53.3V |
| Supply Voltage-Min (Vsup) | 1.45V |
| Speed | 450MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC G2_LE |
| Clock Frequency | 450MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | NO |
| External Data Bus Width | 64 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 3.3V |
| Ethernet | 10/100Mbps (3) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DRAM, SDRAM |
| USB | USB 2.0 (1) |
| Additional Interfaces | I2C, SCC, SMC, SPI, UART, USART |
| Co-Processors/DSP | Communications; RISC CPM |
| Height Seated (Max) | 1.65mm |
| Length | 37.5mm |
| RoHS Status | Non-RoHS Compliant |
MPC8270CZUUPEA Description
The MPC8280, MPC8275, and MPC8270—all members of the Power QUICC II family of integrated communications processors—have thorough information about power considerations, DC/AC electrical characteristics, and AC timing parameters (collectively called the MPC8280 throughout this document).
MPC8270CZUUPEA Features
Dual-issue integer (G2_LE) core
Separate power supply for internal logic and for I/O
Separate PLLs for the G2_LE core and for the communications processor module (CPM)
64-bit data and 32-bit address 60x bus
PCI bridge
The system interface unit (SIU)
A CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
MPC8270CZUUPEA Applications
General-purpose amplifier
Switching applications
Power management
Industrial
