Parameters | |
---|---|
Factory Lead Time | 1 Week |
Package / Case | 256-BBGA |
Surface Mount | YES |
Operating Temperature | 0°C~95°C TA |
Packaging | Tray |
Published | 1999 |
Series | MPC8xx |
JESD-609 Code | e1 |
Part Status | Obsolete |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
Number of Terminations | 256 |
ECCN Code | 3A991.A.2 |
Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
HTS Code | 8542.31.00.01 |
Subcategory | Other uPs/uCs/Peripheral ICs |
Technology | CMOS |
Terminal Position | BOTTOM |
Terminal Form | BALL |
Peak Reflow Temperature (Cel) | 245 |
Supply Voltage | 1.8V |
Terminal Pitch | 1.27mm |
Time@Peak Reflow Temperature-Max (s) | 30 |
Base Part Number | MPC852 |
JESD-30 Code | S-PBGA-B256 |
Supply Voltage-Max (Vsup) | 1.9V |
Power Supplies | 1.83.3V |
Supply Voltage-Min (Vsup) | 1.7V |
Speed | 100MHz |
uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
Clock Frequency | 66MHz |
Bit Size | 32 |
Address Bus Width | 32 |
Boundary Scan | YES |
Low Power Mode | YES |
External Data Bus Width | 32 |
Format | FIXED POINT |
Integrated Cache | YES |
Voltage - I/O | 3.3V |
Ethernet | 10Mbps (1) |
Number of Cores/Bus Width | 1 Core 32-Bit |
Graphics Acceleration | No |
RAM Controllers | DRAM |
Additional Interfaces | HDLC/SDLC, PCMCIA, SPI, UART |
Co-Processors/DSP | Communications; CPM |
Height Seated (Max) | 2.54mm |
Length | 23mm |
RoHS Status | Non-RoHS Compliant |
The MPC852TVR100A is a 0.18-micron derivative of the MPC860 PowerQUICC? family and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852TVR100A has a 1.8-V core and a 3.3-V I/O operation with 5-V TTL compatibility. The MPC852TVR100A integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet routers and hubs, VoIP clients, and WiFi access points.
Embedded MPC8xx core up to 100 MHz
The maximum frequency operation of the external bus is 66 MHz
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Diesel Engine Management
Broadband Modem and Residential Gateway
POS Terminal
Motorcycle Engine Control Unit (ECU) and Small Engine Control
CPE equipment