MPC8533EVTALF
| Parameters | |
|---|---|
| Additional Interfaces | DUART, HSSI, I2C, PCI |
| Co-Processors/DSP | Security; SEC |
| Security Features | Cryptography, Random Number Generator |
| Height Seated (Max) | 2.8mm |
| Length | 29mm |
| RoHS Status | ROHS3 Compliant |
| Package / Case | 783-BBGA, FCBGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~90°C TA |
| Packaging | Tray |
| Published | 2006 |
| Series | MPC85xx |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 783 |
| ECCN Code | 3A001.A.3 |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Supply Voltage | 1V |
| Terminal Pitch | 1mm |
| Base Part Number | MPC8533 |
| JESD-30 Code | S-PBGA-B783 |
| Supply Voltage-Max (Vsup) | 1.05V |
| Supply Voltage-Min (Vsup) | 0.95V |
| Speed | 667MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR |
| Core Processor | PowerPC e500v2 |
| Clock Frequency | 133MHz |
| Bit Size | 32 |
| Address Bus Width | 16 |
| Boundary Scan | YES |
| Low Power Mode | YES |
| External Data Bus Width | 64 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 1.8V 2.5V 3.3V |
| Ethernet | 10/100/1000Mbps (2) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DDR, DDR2 |
MPC8533EVTALF Description
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8533E. This device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer
design specifications.
MPC8533EVTALF Features
256-Kbyte L2 cache/SRAM
— Flexible configuration
— Full ECC support on the 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
– 1, 2, or 4 ways can be configured for stashing only.
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking the entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or externally mastered transactions.
— Global locking and flash clearing are done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately.
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses.
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 36-bit address space.
— Inbound and outbound ATMUs map to larger external address spaces.
– Three inbound windows plus a configuration window on PCI and PCI Express
– Four outbound windows plus default translation for PCI and PCI Express
DDR/DDR2 memory controller
— Programmable timing supporting DDR and DDR2 SDRAM
— 64-bit data interface
