MPC8541EVTAPF
| Parameters | |
|---|---|
| Package / Case | 783-BBGA, FCBGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~105°C TA |
| Packaging | Tray |
| Published | 2002 |
| Series | MPC85xx |
| JESD-609 Code | e2 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 783 |
| ECCN Code | 5A002.A.1 |
| Terminal Finish | TIN COPPER/TIN SILVER |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 1mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | MPC8541 |
| JESD-30 Code | R-PBGA-B783 |
| Supply Voltage-Max (Vsup) | 1.26V |
| Supply Voltage-Min (Vsup) | 1.14V |
| Speed | 833MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC e500 |
| Clock Frequency | 166MHz |
| Bit Size | 32 |
| Address Bus Width | 64 |
| Boundary Scan | YES |
| Low Power Mode | YES |
| External Data Bus Width | 64 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 2.5V 3.3V |
| Ethernet | 10/100/1000Mbps (2) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DDR, SDRAM |
| Additional Interfaces | DUART, I2C, PCI |
| Co-Processors/DSP | Security; SEC |
| Security Features | Cryptography, Random Number Generator |
| Height Seated (Max) | 3.75mm |
| Length | 29mm |
| RoHS Status | ROHS3 Compliant |
MPC8541EVTAPF Description
The MPC8541E integrates a PowerPC? processor core built on Power Architecture? technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8541E is a member of the PowerQUICC? III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8555E PowerQUICC? III Integrated Communications Processor Reference Manual.
MPC8541EVTAPF Features
Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit specially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
