MPC8548EVTAUJB

MPC8548EVTAUJB Description

This section provides a high-level overview of the device's features. The following figure shows the major functional units within the device. Although this document is written from the perspective of the MPC8548E, most of the material applies to the other family members, such as MPC8547E, MPC8545E, and

MPC8543E. When specific differences occur, such as pinout differences and processor frequency ranges, they are identified as such.

MPC8548EVTAUJB Features

512-Kbyte L2 cache/SRAM

— Flexible configuration.

— Full ECC support on the 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

— 1, 2, or 4 ways can be configured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking the entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or externally mastered transactions.

— Global locking and Flash clearing are done through writes to L2 configuration registers

— Instruction and data locks can be Flash cleared separately.

— SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for

smaller-than-cache-line accesses.

Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express

– Four inbound windows plus a default window on RapidIO?

– Four outbound windows plus default translation for PCI/PCI-X and PCI Express

– Eight outbound windows plus default translation for RapidIO with segmentation and

sub-segmentation support

DDR/DDR2 memory controller

— Programmable timing supporting DDR and DDR2 SDRAM

— 64-bit data interface

— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

— DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports

— Full ECC support

— Page mode support

– Up to 16 simultaneous open pages for DDR

– Up to 32 simultaneous open pages for DDR2