MPC860SRZQ50D4
| Parameters | |
|---|---|
| Package / Case | 357-BBGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~95°C TA |
| Packaging | Tray |
| Published | 1995 |
| Series | MPC8xx |
| JESD-609 Code | e0 |
| Part Status | Not For New Designs |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 357 |
| ECCN Code | 3A991.A.2 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| HTS Code | 8542.31.00.01 |
| Subcategory | Microprocessors |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | MPC860 |
| JESD-30 Code | S-PBGA-B357 |
| Supply Voltage-Max (Vsup) | 3.465V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 3.135V |
| Speed | 50MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Clock Frequency | 50MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | YES |
| External Data Bus Width | 32 |
| Format | FIXED POINT |
| Integrated Cache | YES |
| Voltage - I/O | 3.3V |
| Ethernet | 10Mbps (4) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DRAM |
| Additional Interfaces | HDLC/SDLC, I2C, IrDA, PCMCIA, SPI, TDM, UART/USART |
| Co-Processors/DSP | Communications; CPM |
| Height Seated (Max) | 2.52mm |
| Length | 25mm |
| RoHS Status | Non-RoHS Compliant |
MPC860SRZQ50D4 Description
The MPC860SRZQ50D4 is a PowerPC? architecture-based quad integrated communications controller (PowerQUICC?). The CPU on the MPC860SRZQ50D4 is the MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. The MPC860SRZQ50D4 PowerQUICC? offers an integrated processor and peripheral solution that can be used in a variety of communications and networking controller applications.
MPC860SRZQ50D4 Features
4Kb Instruction Cache; MPC860P - 16Kb Instruction Cache
4Kb Data Cache; MPC860P - 8Kb Data Cache
8Kb Dual Port RAM
Instruction and Data MMUs
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
32 Address Lines
Complete Static Design (040 MHz Operation)
Memory Controller (Eight Banks)
MPC860SRZQ50D4 Applications
Automotive
Advanced driver assistance systems (ADAS)
Communications equipment
Broadband fixed line access
Enterprise systems
Enterprise machine
