Parameters | |
---|---|
Factory Lead Time | 1 Week |
Package / Case | 357-BBGA |
Surface Mount | YES |
Operating Temperature | 0°C~95°C TA |
Packaging | Tray |
Published | 1999 |
Series | MPC8xx |
JESD-609 Code | e0 |
Part Status | Obsolete |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
Number of Terminations | 357 |
ECCN Code | 3A991.A.2 |
Terminal Finish | Tin/Lead (Sn/Pb) |
HTS Code | 8542.31.00.01 |
Subcategory | Microprocessors |
Technology | CMOS |
Terminal Position | BOTTOM |
Terminal Form | BALL |
Peak Reflow Temperature (Cel) | 220 |
Supply Voltage | 1.8V |
Terminal Pitch | 1.27mm |
Time@Peak Reflow Temperature-Max (s) | 30 |
Base Part Number | MPC866 |
JESD-30 Code | S-PBGA-B357 |
Supply Voltage-Max (Vsup) | 1.9V |
Power Supplies | 1.83.3V |
Supply Voltage-Min (Vsup) | 1.7V |
Speed | 133MHz |
uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
Clock Frequency | 133MHz |
Bit Size | 32 |
Address Bus Width | 32 |
Boundary Scan | YES |
Low Power Mode | YES |
External Data Bus Width | 32 |
Format | FIXED POINT |
Integrated Cache | YES |
Voltage - I/O | 3.3V |
Ethernet | 10Mbps (4), 10/100Mbps (1) |
Number of Cores/Bus Width | 1 Core 32-Bit |
Graphics Acceleration | No |
RAM Controllers | DRAM |
Additional Interfaces | HDLC/SDLC, I2C, IrDA, PCMCIA, SPI, TDM, UART/USART |
Co-Processors/DSP | Communications; CPM |
Height Seated (Max) | 2.52mm |
Length | 25mm |
RoHS Status | Non-RoHS Compliant |
MPC866PZP133A PowerQUICC? process is a 0.18-micron version of the MPC862 PowerQUICC? Family and can operate up to 133 MHz on the MPC8xx core with a 66 MHz external bus. The MPC866PZP133A has a 1.8 V core and a 3.3 V I/O operation with 5 V TTL compatibilty. The MPC866PZP133A Integrated Communications Controller Family is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in both communications and networking systems.
The maximum frequency operation of the external bus is 66 MHz
Single-issue, 32-bit core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
A memory controller (eight banks)
General-purpose timers
Fast Ethernet controller (FEC)
Battery Management System (BMS)
Diesel Engine Management
Electric Power Steering (EPS)
Gateway
Motorcycle Engine Control Unit (ECU) and Small Engine Control
Broadband Modem and Residential Gateway
POS Terminal