N74F112D,602
| Parameters | |
|---|---|
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74F112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | F/FAST |
| Current - Quiescent (Iq) | 21mA |
| Current - Output High, Low | 1mA 20mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Propagation Delay (tpd) | 7.5 ns |
| fmax-Min | 80 MHz |
| Max Frequency@Nom-Sup | 80000000Hz |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Published | 1999 |
| Series | 74F |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
N74F112D,602 Overview
The package is in the form of 16-SOIC (0.154, 3.90mm Width). As part of the package Tube, it is embedded. Currently, the output is configured to use Differential. It is configured with the trigger Negative Edge. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 4.5V~5.5V. Temperature is set to 0°C~70°C TA. A flip flop of this type is classified as a JK Type. It is a type of FPGA belonging to the 74F series. A frequency of 100MHzshould not be exceeded by its output. A total of 2elements are present in it. This process consumes 21mA quiescents. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This D latch belongs to the family of 74F112. A voltage of 5V provides power to the D latch. An electronic device belonging to the family F/FASTcan be found here. The part you are looking for is included in FF/Latches. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. The supply voltage (Vsup) should be maintained above 4.5V for normal operation. There are 5V power supplies attached to it.
N74F112D,602 Features
Tube package
74F series
5V power supplies
N74F112D,602 Applications
There are a lot of NXP USA Inc. N74F112D,602 Flip Flops applications.
- Individual Asynchronous Resets
- ESCC
- Consumer
- Asynchronous counter
- Test & Measurement
- Counters
- Computing
- Modulo – n – counter
- Storage Registers
- Pattern generators
