N74F112N,602
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Published | 1999 |
| Series | 74F |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74F112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | F/FAST |
| Current - Quiescent (Iq) | 21mA |
| Current - Output High, Low | 1mA 20mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Propagation Delay (tpd) | 7.5 ns |
| fmax-Min | 80 MHz |
| Max Frequency@Nom-Sup | 80000000Hz |
| RoHS Status | ROHS3 Compliant |
N74F112N,602 Overview
As a result, it is packaged as 16-DIP (0.300, 7.62mm). The package Tubecontains it. This output is configured with Differential. It is configured with a trigger that uses a value of Negative Edge. There is an electronic component mounted in the way of Through Hole. A 4.5V~5.5Vsupply voltage is required for it to operate. It is at 0°C~70°C TAdegrees Celsius that the system is operating. This electronic flip flop is of type JK Type. It belongs to the 74Fseries of FPGAs. A frequency of 100MHzshould be the maximum output frequency. The element count is 2 . It consumes 21mA of quiescent current without being affected by external factors. A total of 16terminations have been recorded. JK flip flop belongs to 74F112 family. It is powered by a voltage of 5V . F/FASTis the family of this D flip flop. There is a FF/Latchesbase part number assigned to the RS flip flops. Vsup reaches 5.5V, the maximal supply voltage. For normal operation, the supply voltage (Vsup) should be above 4.5V. An electrical current of 5V volts is applied to it.
N74F112N,602 Features
Tube package
74F series
5V power supplies
N74F112N,602 Applications
There are a lot of NXP USA Inc. N74F112N,602 Flip Flops applications.
- Balanced Propagation Delays
- Frequency division
- Divide a clock signal by 2 or 4
- Pattern generators
- Asynchronous counter
- Digital electronics systems
- Consumer
- Guaranteed simultaneous switching noise level
- ATE
- Bus hold
