Parameters |
Factory Lead Time |
1 Week |
Lifecycle Status |
ACTIVE (Last Updated: 2 days ago) |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
8-VFSOP (0.091, 2.30mm Width) |
Number of Pins |
8 |
Weight |
30mg |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tape & Reel (TR) |
Published |
2005 |
Series |
7SP |
Pbfree Code |
yes |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
8 |
ECCN Code |
EAR99 |
Type |
D-Type |
Subcategory |
FF/Latches |
Packing Method |
TAPE AND REEL |
Technology |
CMOS |
Voltage - Supply |
0.9V~3.6V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Supply Voltage |
1.2V |
Terminal Pitch |
0.5mm |
Base Part Number |
7SP74 |
Function |
Set(Preset) and Reset |
Output Type |
Differential |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
3.6V |
Supply Voltage-Min (Vsup) |
0.9V |
Number of Channels |
1 |
Load Capacitance |
30pF |
Output Current |
2.6mA |
Number of Bits |
1 |
Clock Frequency |
150MHz |
Propagation Delay |
34 ns |
Turn On Delay Time |
24 ns |
Family |
P |
Logic Function |
AND, D-Type, Flip-Flop |
Current - Quiescent (Iq) |
900nA |
Current - Output High, Low |
2.6mA 2.6mA |
Max I(ol) |
0.0005 A |
Max Propagation Delay @ V, Max CL |
8ns @ 3.3V, 30pF |
Trigger Type |
Positive Edge |
Input Capacitance |
2pF |
fmax-Min |
250 MHz |
Clock Edge Trigger Type |
Positive Edge |
Height |
700μm |
Length |
2mm |
Width |
2.3mm |
Radiation Hardening |
No |
REACH SVHC |
No SVHC |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
NC7SP74K8X Overview
It is packaged in the way of 8-VFSOP (0.091, 2.30mm Width). It is contained within the Tape & Reel (TR)package. There is a Differentialoutput configured with it. It is configured with a trigger that uses Positive Edge. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates at 0.9V~3.6Vvolts. It is operating at -40°C~85°C TA. A flip flop of this type is classified as a D-Type. It is a type of FPGA belonging to the 7SP series. This D flip flop should not have a frequency greater than 150MHz. As a result, it consumes 900nA of quiescent current without being affected by external factors. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. It is a member of the 7SP74 family. It is powered by a voltage of 1.2V . This JK flip flop has a 2pFfarad input capacitance. A device of this type belongs to the family of P. There is an electronic component mounted in the way of Surface Mount. There are 8pins on it. There is a clock edge trigger type of Positive Edgeon this device. It is included in FF/Latches. The flip flop is designed with 1bits. 3.6Vis the maximum supply voltage (Vsup). Keeping the supply voltage (Vsup) above 0.9V is necessary for normal operation. In view of its reliability, this D flip flop is a good fit for TAPE AND REEL. In addition to its maximum design flexibility, the output current of the T flip flop is 2.6mA. 1is the number of channels.
NC7SP74K8X Features
Tape & Reel (TR) package
7SP series
8 pins
1 Bits
NC7SP74K8X Applications
There are a lot of ON Semiconductor NC7SP74K8X Flip Flops applications.
- Test & Measurement
- Set-reset capability
- Single Down Count-Control Line
- Dynamic threshold performance
- Bus hold
- Guaranteed simultaneous switching noise level
- Modulo – n – counter
- Parallel data storage
- Buffered Clock
- Bounce elimination switch