NLSF1174MNR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-VFQFN Exposed Pad |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2006 |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 4.5V |
| Terminal Pitch | 0.5mm |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | NLSF1174 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 7 |
| Load Capacitance | 50pF |
| Number of Bits | 6 |
| Clock Frequency | 35MHz |
| Propagation Delay | 110 ns |
| Turn On Delay Time | 19 ns |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.00002 A |
| Max Propagation Delay @ V, Max CL | 19ns @ 6V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 10pF |
| Number of Output Lines | 6 |
| Clock Edge Trigger Type | Positive Edge |
| Length | 3mm |
| Width | 3mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
NLSF1174MNR2 Overview
The package is in the form of 16-VFQFN Exposed Pad. It is included in the package Tape & Reel (TR). This output is configured with Non-Inverted. It is configured with a trigger that uses Positive Edge. Surface Mountis in the way of this electric part. It operates with a supply voltage of 2V~6V. -55°C~125°C TAis the operating temperature. D-Typedescribes this flip flop. It should not exceed 35MHzin terms of its output frequency. The list contains 1 elements. There is 4μA quiescent consumption. It has been determined that there have been 16 terminations. JK flip flop belongs to NLSF1174 family. A voltage of 4.5V is used to power it. A JK flip flop with a 10pFfarad input capacitance is used here. There is an electronic part mounted in the way of Surface Mount. A Positive Edgeclock edge trigger is used in this device. This device is part of the FF/Latchesbase part number family. This flip flop is designed with 6 Bits. In this case, the maximum supply voltage (Vsup) reaches 6V. A normal operating voltage (Vsup) should remain above 2V. To achieve this superior flexibility, 7 circuits are used. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TAPE AND REEL. There are 6 output Lines, which generate the binary equivalent of the input line whose value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or “B. C. D” (binary coded decimal) output code.
NLSF1174MNR2 Features
Tape & Reel (TR) package
6 Bits
NLSF1174MNR2 Applications
There are a lot of ON Semiconductor NLSF1174MNR2 Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Modulo – n – counter
- Parallel data storage
- Common Clocks
- Event Detectors
- Shift registers
- QML qualified product
- Reduced system switching noise
- Buffered Clock
- Set-reset capability
