NLV74HC174ADG
| Parameters | |
|---|---|
| Clock Frequency | 35MHz |
| Propagation Delay | 27 ns |
| Quiescent Current | 4μA |
| Family | HC/UH |
| Halogen Free | Halogen Free |
| Current - Output High, Low | 5.2mA 5.2mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.004 A |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 27ns @ 6V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 10pF |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 20000000Hz |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Published | 2006 |
| Series | Automotive, AEC-Q100 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
NLV74HC174ADG Overview
16-SOIC (0.154, 3.90mm Width)is the packaging method. There is an embedded version in the package Tube. T flip flop is configured with an output of Non-Inverted. This trigger uses the value Positive Edge. Surface Mountis occupied by this electronic component. The JK flip flop operates at 2V~6Vvolts. In the operating environment, the temperature is -55°C~125°C TA. D-Typeis the type of this D latch. This type of FPGA is a part of the Automotive, AEC-Q100 series. There should be no greater frequency than 35MHzon its output. D latch consists of 1 elements. Terminations are 16. It is powered from a supply voltage of 5V. This JK flip flop has a 10pFfarad input capacitance. In this case, the D flip flop belongs to the HC/UHfamily. It is mounted in the way of Surface Mount. With its 16pins, it is designed to work with most electronic flip flops. There is a clock edge trigger type of Positive Edgeon this device. There is a base part number FF/Latchesfor the RS flip flops. As soon as Vsup reaches 6V, the maximum supply voltage is reached. The supply voltage (Vsup) should be maintained above 2V for normal operation. Considering its reliability, this T flip flop is well suited for RAIL. There is a consumption of 4μAof quiescent current from it.
NLV74HC174ADG Features
Tube package
Automotive, AEC-Q100 series
16 pins
NLV74HC174ADG Applications
There are a lot of ON Semiconductor NLV74HC174ADG Flip Flops applications.
- CMOS Process
- Single Up Count-Control Line
- Data transfer
- Counters
- Shift Registers
- 2 – Bit synchronous counter
- Clock pulse
- Supports Live Insertion
- Load Control
- Circuit Design
