Parameters |
Factory Lead Time |
1 Week |
Lifecycle Status |
ACTIVE (Last Updated: 3 days ago) |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
20-TSSOP (0.173, 4.40mm Width) |
Operating Temperature |
-55°C~125°C TA |
Packaging |
Tape & Reel (TR) |
Published |
2014 |
Series |
Automotive, AEC-Q100 |
JESD-609 Code |
e4 |
Pbfree Code |
yes |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
20 |
Type |
D-Type |
Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au) |
Technology |
CMOS |
Voltage - Supply |
2V~3.6V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
3.3V |
Terminal Pitch |
0.65mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
JESD-30 Code |
R-PDSO-G20 |
Function |
Standard |
Output Type |
Tri-State, Non-Inverted |
Number of Elements |
1 |
Supply Voltage-Max (Vsup) |
3.6V |
Supply Voltage-Min (Vsup) |
2V |
Number of Ports |
2 |
Clock Frequency |
150MHz |
Propagation Delay |
8.5 ns |
Quiescent Current |
10μA |
Family |
LVC/LCX/Z |
Output Characteristics |
3-STATE |
Current - Output High, Low |
24mA 24mA |
Output Polarity |
TRUE |
Number of Bits per Element |
8 |
Max Propagation Delay @ V, Max CL |
8.5ns @ 3.3V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
7pF |
Clock Edge Trigger Type |
Positive Edge |
Length |
6.5mm |
Width |
4.4mm |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
NLV74LCX574DTR2G Overview
It is packaged in the way of 20-TSSOP (0.173, 4.40mm Width). D flip flop is embedded in the Tape & Reel (TR) package. T flip flop uses Tri-State, Non-Invertedas the output. It is configured with the trigger Positive Edge. Surface Mountis in the way of this electric part. The supply voltage is set to 2V~3.6V. Currently, the operating temperature is -55°C~125°C TA. A flip flop of this type is classified as a D-Type. It belongs to the Automotive, AEC-Q100series of FPGAs. You should not exceed 150MHzin its output frequency. The element count is 1 . There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. An input voltage of 3.3Vpowers the D latch. A JK flip flop with a 7pFfarad input capacitance is used here. A device of this type belongs to the family of LVC/LCX/Z. This electronic part is mounted in the way of Surface Mount. The clock edge trigger type for this device is Positive Edge. It reaches the maximum supply voltage (Vsup) at 3.6V. For normal operation, the supply voltage (Vsup) should be kept above 2V. A D flip flop with 2embedded ports is available. As a result, it consumes 10μA of quiescent current without being affected by external factors.
NLV74LCX574DTR2G Features
Tape & Reel (TR) package
Automotive, AEC-Q100 series
NLV74LCX574DTR2G Applications
There are a lot of ON Semiconductor NLV74LCX574DTR2G Flip Flops applications.
- Latch
- Memory
- Reduced system switching noise
- Frequency Dividers
- ESD protection
- Balanced Propagation Delays
- Clock pulse
- Guaranteed simultaneous switching noise level
- Latch-up performance
- Patented noise