P4080NSE1PNB
| Parameters | |
|---|---|
| Operating Temperature | 0°C~105°C TA |
| Packaging | Tray |
| Published | 2008 |
| Series | QorIQ P4 |
| JESD-609 Code | e1 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| ECCN Code | 5A002.A |
| Terminal Finish | TIN SILVER COPPER |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 1V |
| Terminal Pitch | 1mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | P4080 |
| JESD-30 Code | S-PBGA-B1295 |
| Supply Voltage-Max (Vsup) | 1.05V |
| Supply Voltage-Min (Vsup) | 0.95V |
| Speed | 1.5GHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC e500mc |
| Clock Frequency | 133.3MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | YES |
| External Data Bus Width | 16 |
| Format | FIXED POINT |
| Integrated Cache | YES |
| Voltage - I/O | 1.8V 2.5V 3.3V |
| Ethernet | 1Gbps (8), 10Gbps (2) |
| Number of Cores/Bus Width | 8 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DDR2, DDR3 |
| USB | USB 2.0 + PHY (2) |
| Additional Interfaces | DUART, I2C, MMC/SD, RapidIO, SPI |
| Co-Processors/DSP | Security; SEC 4.0 |
| Security Features | Boot Security, Cryptography, Random Number Generator, Secure Fusebox |
| Height Seated (Max) | 3.53mm |
| Length | 37.5mm |
| RoHS Status | ROHS3 Compliant |
| Package / Case | 1295-BBGA, FCBGA |
| Surface Mount | YES |
P4080NSE1PNB Description
The P4080NSE1PNB multicore processor, the first product offered in the QorIQ P4 platform series delivers industry-leading performance in the under 30-watt power category. P4080NSE1PNB combines eight Power Architecture e500mc cores operating at frequencies up to 1.5 GHz with high-performance datapath acceleration logic, as well as networking I/O and other peripheral bus interfaces.
P4080NSE1PNB Features
Eight high-performance Power Architecture e500mc cores, each with a 32 KB instruction and data L1 cache and a private 128 KB L2 cache
2 MB shared L3 CoreNet platform cache
Hierarchical interconnect fabric
Two 64-bit DDR2/DDR3 SDRAM memory controllers with ECC and interleaving support
Additional peripheral interfaces
Multicore programmable interrupt controller (PIC)
Two 4-channel DMA engines
P4080NSE1PNB Applications
Industrial
Appliances
Enterprise systems
Enterprise machine
Personal electronics
Tablets
