SN65LVDS101DG4
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Weight | 75.891673mg |
| Operating Temperature | -40°C~85°C |
| Packaging | Tube |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | Buffer, ReDriver |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | Line Driver or Receivers |
| Max Power Dissipation | 481mW |
| Technology | BIPOLAR |
| Voltage - Supply | 3V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Number of Functions | 1 |
| Supply Voltage | 3.3V |
| Base Part Number | 65LVDS101 |
| Output | LVPECL |
| Pin Count | 8 |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 1 |
| Operating Supply Current | 30mA |
| Nominal Supply Current | 32mA |
| Power Dissipation | 481mW |
| Output Current | 12μA |
| Propagation Delay | 900 ps |
| Turn On Delay Time | 900 ps |
| Logic Function | Translator |
| Input | CML, LVDS, LVPECL |
| Driver Number of Bits | 1 |
| Receiver Number of Bits | 1 |
| Interface Standard | EIA-644-A; TIA-644-A |
| Receive Delay-Max | 0.9 ns |
| Data Rate (Max) | 2Gbps |
| Transmit Delay-Max | 0.9 ns |
| Supply Voltage1-Nom | 3.3V |
| Delay Time | 630ps |
| Capacitance - Input | 0.6pF |
| Length | 4.9mm |
| Width | 3.9mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN65LVDS101DG4 Overview
Transport is made easy with power buffer packaging in 8-SOIC (0.154, 3.90mm Width).The package is ready for power buffer in Tube pieces.An easy-to-adjust universaal mout for easy adjustability.The type Buffer, ReDriver is typical.To operate, this op amp buffer needs 3V~3.6V voltage.The system facilitates the input of CML, LVDS, LVPECL.It is recommended to set the operating temperature to -40°C~85°C to prevent malfunctions.You can also search with "65LVDS101" if you want to find more pin-to-pin solutions that meet your special needs.There are two 8 terminals on the op amp buffer and you can find them at the end of the op amp buffer.The peak reflow temperature of the material is 260.Powered by a 3.3V voltage, the splitter is capable of performing many demanding tasks due to its dependable supply.A Power buffer's pinout is determined by the number of pins that it has and starts with 8.Outputs are in LVPECL.Pins on its 8 axis are present.This board has a Surface Mount hole for mounting on a PCB or other board.In the industry, other Line Driver or Receivers like the power buffer play an important role.Voltage 30mA is needed to operate this power buffer.It is necessary for 3.3V operating supply voltage to function normally.Receiver uses 1-Bit technology.There is a maximum dissipation of 481mW of power from this splitter.Normal supply current for the splitter is 32mA.A 1 element interface repeater signal is what we are dealing with here.Spliter output should be 12μA at the moment.
SN65LVDS101DG4 Features
A standard Line Driver or Receivers.
1-Bit receiver.
SN65LVDS101DG4 Applications
There are a lot of Texas Instruments SN65LVDS101DG4 Signal Buffers, Repeaters, Splitters applications.
- Test Equipment
- PECL-to-LVDS Translation
- Cellular Phone Base Stations
- Servers
- Industrial PCs
- Clock Distribution
- Network Switches/Routers
- Network Switches/Routers
- Industrial Server
- Loopback
