Parameters |
Reach Compliance Code |
unknown |
JESD-30 Code |
R-PDSO-G20 |
Output Type |
Tri-State |
Circuit |
8:8 |
Supply Voltage-Max (Vsup) |
5.5V |
Supply Voltage-Min (Vsup) |
4.5V |
Number of Ports |
2 |
Number of Bits |
8 |
Family |
ACT |
Output Characteristics |
3-STATE |
Current - Output High, Low |
24mA 24mA |
Logic Type |
D-Type Transparent Latch |
Output Polarity |
INVERTED |
Independent Circuits |
1 |
Delay Time - Propagation |
6.5ns |
Height Seated (Max) |
2mm |
Length |
7.2mm |
Width |
5.3mm |
RoHS Status |
ROHS3 Compliant |
Mounting Type |
Surface Mount |
Package / Case |
20-SSOP (0.209, 5.30mm Width) |
Surface Mount |
YES |
Operating Temperature |
-40°C~85°C |
Packaging |
Tape & Reel (TR) |
Series |
74ACT |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
20 |
Technology |
CMOS |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Number of Functions |
1 |
Supply Voltage |
5V |
Terminal Pitch |
0.65mm |
SN74ACT563DBR Overview
The 20-SSOP (0.209, 5.30mm Width) package contains it. Tape & Reel (TR) is the packaging method. It uses Tri-State as its output configuration. D-Type Transparent Latch is the logic type of this electrical device. The way in which this electronic part is mounted is Surface Mount. It operates with a supply voltage of 4.5V~5.5V. A temperature of -40°C~85°C is used for operation. An FPGA in this series belongs to the 74ACT family. It is designed with 8 bits. As far as this device is concerned, it has no terminations. The device works with a voltage of 5V for its supply voltage. In the world of electronics, this electronic device belongs to the family of ACT. 2 ports are available on this device. Vsup reaches 5.5V as the maximum supply voltage. (Vsup) should be greater than 4.5V.
SN74ACT563DBR Features
20-SSOP (0.209, 5.30mm Width) package
74ACT series
8 Bits
SN74ACT563DBR Applications
There are a lot of Rochester Electronics, LLC SN74ACT563DBR Latches applications.
- A/D and D/A conversion
- Parallel data storage
- Bus system register with enable parallel lines at bus side
- Phase comparator
- Pseudo-random code generators
- Display
- Storage
- Clocks
- Shift left with parallel loading
- Parallel-to-Serial Data Conversion