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SN74ALVCH162373GR

D-Type, Latch 1.65V~3.6V 16 Bits Tri-State Latches 74ALVCH Series 74ALVCH162373 48 Pins DUAL CMOS 48-TFSOP (0.240, 6.10mm Width)


  • Manufacturer: Texas Instruments
  • Nocochips NO: 815-SN74ALVCH162373GR
  • Package: 48-TFSOP (0.240, 6.10mm Width)
  • Datasheet: -
  • Stock: 297
  • Description: D-Type, Latch 1.65V~3.6V 16 Bits Tri-State Latches 74ALVCH Series 74ALVCH162373 48 Pins DUAL CMOS 48-TFSOP (0.240, 6.10mm Width)(Kg)

Details

Tags

Parameters
Factory Lead Time 1 Week
Lifecycle Status ACTIVE (Last Updated: 3 days ago)
Contact Plating Gold
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 48-TFSOP (0.240, 6.10mm Width)
Number of Pins 48
Weight 223.195796mg
Operating Temperature -40°C~85°C
Packaging Tape & Reel (TR)
Series 74ALVCH
JESD-609 Code e4
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 48
ECCN Code EAR99
Subcategory FF/Latches
Packing Method TR
Technology CMOS
Voltage - Supply 1.65V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Number of Functions 2
Supply Voltage 1.8V
Terminal Pitch 0.5mm
Base Part Number 74ALVCH162373
Pin Count 48
Output Type Tri-State
Number of Elements 2
Circuit 8:8
Polarity Non-Inverting
Supply Voltage-Min (Vsup) 1.65V
Load Capacitance 50pF
Number of Ports 2
Output Current 12mA
Number of Bits 16
Propagation Delay 4 ns
Quiescent Current 40μA
Turn On Delay Time 1 ns
Family ALVC/VCX/A
Logic Function D-Type, Latch
Current - Output High, Low 12mA 12mA
Logic Type D-Type Transparent Latch
Control Type ENABLE LOW/HIGH
Power Supply Current-Max (ICC) 0.04mA
Number of Output Lines 3
Count Direction UNIDIRECTIONAL
Translation N/A
Height 1.2mm
Length 12.5mm
Width 6.1mm
Thickness 1.15mm
Radiation Hardening No
REACH SVHC No SVHC
RoHS Status ROHS3 Compliant
Lead Free Lead Free

SN74ALVCH162373GR Overview


The package in which it is embedded is named 48-TFSOP (0.240, 6.10mm Width). The package is in the form of Tape & Reel (TR). Tri-State is used for the output it is configured with. This electrical device has the logic type D-Type Transparent Latch. Mounting this electronic component follows the Surface Mount method. It operates at a voltage of 1.65V~3.6V. A temperature of -40°C~85°C is set as the operating temperature. The 74ALVCH series of FPGAs is the one this FPGA belongs to. It is designed with 16 bits. As far as this device is concerned, it has no terminations. As a member of the 74ALVCH162373 family, it falls under that category. The device works with a voltage of 1.8V for its supply voltage. It has 48 pins that makes it easy to use. It is part of the family of electronic devices called ALVC/VCX/A. The 48 pins are designed into it. The electronic part is mounted in a way that corresponds to Surface Mount. 2 ports are available on this device. This part can be found within the FF/Latches subcategory. Ensure that the supply voltage (Vsup) is greater than 1.65V. As a result of its reliable performance, it is well suited for TR. Due to its 12mA output current, it offers maximum design flexibility. There are 3 output Lines, which generate the binary equivalent of the input line whose value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or “B. C. D” (binary coded decimal) output code. The current consumed by the device is 40μA volts in quiescent mode, which cannot be affected by external factors. A total of 2 elements make up this object. Maximum power supply (ICC) for its operation is 0.04mA.

SN74ALVCH162373GR Features


48-TFSOP (0.240, 6.10mm Width) package
74ALVCH series
16 Bits
74ALVCH162373 family
48 pin count
48 pins
2 elements

SN74ALVCH162373GR Applications


There are a lot of Texas Instruments SN74ALVCH162373GR Latches applications.

  • Multi-line decoders
  • Bus system register with enable parallel lines at bus side
  • Pseudo-random code generators
  • Automotive Infotainment
  • Display
  • PCs and Notebooks
  • Serial Output Register
  • Hammer Device Information
  • Up-Down Johnson
  • Parallel data synchronization

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