Parameters |
Additional Feature |
WITH PRESET |
Subcategory |
FF/Latches |
Technology |
TTL |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
5V |
Base Part Number |
74AS876 |
Function |
Master Reset |
Output Type |
Tri-State, Inverted |
Operating Supply Voltage |
5V |
Number of Elements |
2 |
Polarity |
Inverting |
Load Capacitance |
50pF |
Number of Ports |
2 |
Output Current |
48mA |
Number of Bits |
8 |
Clock Frequency |
80MHz |
Propagation Delay |
10.5 ns |
Turn On Delay Time |
3 ns |
Family |
AS |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
142mA |
Output Characteristics |
3-STATE |
Current - Output High, Low |
15mA 48mA |
Number of Bits per Element |
4 |
Max Propagation Delay @ V, Max CL |
10.5ns @ 5V, 50pF |
Trigger Type |
Positive Edge |
Number of Output Lines |
1 |
Clock Edge Trigger Type |
Positive Edge |
Width |
7.5mm |
Radiation Hardening |
No |
REACH SVHC |
No SVHC |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Contains Lead |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
24-SOIC (0.295, 7.50mm Width) |
Number of Pins |
24 |
Weight |
624.398247mg |
Operating Temperature |
0°C~70°C TA |
Packaging |
Tube |
Series |
74AS |
JESD-609 Code |
e4 |
Pbfree Code |
yes |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
24 |
Termination |
SMD/SMT |
Type |
D-Type |
Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au) |
SN74AS876DW Overview
It is packaged in the way of 24-SOIC (0.295, 7.50mm Width). It is included in the package Tube. T flip flop uses Tri-State, Invertedas the output. In the configuration of the trigger, Positive Edgeis used. Surface Mountis positioned in the way of this electronic part. It operates with a supply voltage of 4.5V~5.5V. A temperature of 0°C~70°C TAis considered to be the operating temperature. The type of this D latch is D-Type. This type of FPGA is a part of the 74AS series. Its output frequency should not exceed 80MHz. In total, it contains 2 elements. It consumes 142mA of quiescent There are 24 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This D latch belongs to the family of 74AS876. An input voltage of 5Vpowers the D latch. In terms of electronic devices, this device belongs to the ASfamily of devices. It is mounted by the way of Surface Mount. Basically, it is designed with a set of 24 pins. This device's clock edge trigger type is Positive Edge. This part is included in FF/Latches. The flip flop is designed with 8bits. The D flip flop has no ports embedded. In order to achieve high efficiency, the supply voltage should be maintained at 5V. With a current output of 48mA , it offers maximum design flexibility. There are 1 output Lines, which generate the binary equivalent of the input line whose value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or “B. C. D” (binary coded decimal) output code. Additionally, you may refer to the additional WITH PRESET of the electronic flip flop.
SN74AS876DW Features
Tube package
74AS series
24 pins
8 Bits
SN74AS876DW Applications
There are a lot of Texas Instruments SN74AS876DW Flip Flops applications.
- Memory
- Data Synchronizers
- Latch-up performance
- Shift registers
- Pattern generators
- Test & Measurement
- Bus hold
- Individual Asynchronous Resets
- ESD protection
- Clock pulse