SN74AUC1G79YZAR
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 5-XFBGA, DSBGA |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUC |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 5 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 0.8V~2.7V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUC1G79 |
| JESD-30 Code | R-PBGA-B5 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 2.7V |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 275MHz |
| Turn On Delay Time | 5 ns |
| Family | AUC |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 9mA 9mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.005 A |
| Max Propagation Delay @ V, Max CL | 1.8ns @ 2.5V, 30pF |
| Prop. Delay@Nom-Sup | 3.9 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| Propagation Delay (tpd) | 3.9 ns |
| fmax-Min | 275 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 200000000Hz |
| Height Seated (Max) | 0.5mm |
| Width | 0.9mm |
| RoHS Status | ROHS3 Compliant |
SN74AUC1G79YZAR Overview
5-XFBGA, DSBGAis the way it is packaged. The Tape & Reel (TR)package contains it. T flip flop uses Non-Invertedas the output. This trigger is configured to use Positive Edge. There is an electronic component mounted in the way of Surface Mount. A 0.8V~2.7Vsupply voltage is required for it to operate. The operating temperature is -40°C~85°C TA. D-Typeis the type of this D latch. In this case, it is a type of FPGA belonging to the 74AUC series. A frequency of 275MHzshould not be exceeded by its output. A total of 1 elements are present. There is a consumption of 10μAof quiescent energy. There are 5 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The object belongs to the 74AUC1G79 family. The power supply voltage is 1.2V. This JK flip flop has a 2.5pFfarad input capacitance. In this case, the D flip flop belongs to the AUCfamily. Surface Mount mounts this electronic component. It has a clock edge trigger type of Positive Edge. This device is part of the FF/Latchesbase part number family. It is designed with 1bits. As soon as Vsup reaches 2.7V, the maximum supply voltage is reached. For normal operation, the supply voltage (Vsup) should be above 0.8V. In view of its reliability, this D flip flop is a good fit for TAPE AND REEL.
SN74AUC1G79YZAR Features
Tape & Reel (TR) package
74AUC series
1 Bits
SN74AUC1G79YZAR Applications
There are a lot of Texas Instruments SN74AUC1G79YZAR Flip Flops applications.
- Balanced 24 mA output drivers
- ATE
- Single Up Count-Control Line
- ESD protection
- Communications
- Storage Registers
- Storage registers
- Test & Measurement
- Frequency Divider circuits
- QML qualified product
