SN74AUC1G80DCKR
| Parameters | |
|---|---|
| Weight | 2.494758mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74AUC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 5 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~2.7V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Base Part Number | 74AUC1G80 |
| Function | Standard |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 1 |
| Output Current | 9mA |
| Number of Bits | 1 |
| Clock Frequency | 275MHz |
| Propagation Delay | 2.4 ns |
| Turn On Delay Time | 5 ns |
| Family | AUC |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 9mA 9mA |
| Max I(ol) | 0.009 A |
| Max Propagation Delay @ V, Max CL | 1.8ns @ 2.5V, 30pF |
| Prop. Delay@Nom-Sup | 3.9 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| Number of Input Lines | 2 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1.1mm |
| Length | 2mm |
| Width | 1.25mm |
| Thickness | 900μm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 5-TSSOP, SC-70-5, SOT-353 |
| Number of Pins | 5 |
SN74AUC1G80DCKR Overview
5-TSSOP, SC-70-5, SOT-353is the way it is packaged. D flip flop is included in the Cut Tape (CT)package. T flip flop uses Invertedas the output. There is a trigger configured with Positive Edge. There is an electric part mounted in the way of Surface Mount. A voltage of 0.8V~2.7Vis used as the supply voltage. In this case, the operating temperature is -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. JK flip flop belongs to the 74AUCseries of FPGAs. There should be no greater frequency than 275MHzon its output. It consumes 10μA of quiescent Terminations are 5. You can search similar parts based on 74AUC1G80. It is powered from a supply voltage of 1.2V. A JK flip flop with a 2.5pFfarad input capacitance is used here. In this case, the D flip flop belongs to the AUCfamily. It is mounted by the way of Surface Mount. It is designed with 5 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. This part is included in FF/Latches. It is designed with 1bits. The supply voltage (Vsup) should be kept above 0.8V for normal operation. In order to achieve its superior flexibility, 1 circuits are used. This D flip flop is well suited for TR based on its reliable performance. As a result of its output current of 9mA, it is very flexible in terms of design. This input has 2lines in it.
SN74AUC1G80DCKR Features
Cut Tape (CT) package
74AUC series
5 pins
1 Bits
SN74AUC1G80DCKR Applications
There are a lot of Texas Instruments SN74AUC1G80DCKR Flip Flops applications.
- Balanced Propagation Delays
- Dynamic threshold performance
- Set-reset capability
- Instrumentation
- Buffered Clock
- Event Detectors
- Data Synchronizers
- Test & Measurement
- Synchronous counter
- Safety Clamp
