SN74AUC2G79YZPR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFBGA, DSBGA |
| Number of Pins | 8 |
| Weight | 2.296311mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUC |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~2.7V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUC2G79 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Number of Circuits | 2 |
| Clock Frequency | 275MHz |
| Propagation Delay | 1.8 ns |
| Quiescent Current | 10μA |
| Turn On Delay Time | 5 ns |
| Family | AUC |
| Current - Output High, Low | 9mA 9mA |
| Max I(ol) | 0.009 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 1.8ns @ 2.5V, 30pF |
| Prop. Delay@Nom-Sup | 3.9 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 500μm |
| Length | 1.25mm |
| Width | 2.25mm |
| Thickness | 310μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUC2G79YZPR Overview
The package is in the form of 8-XFBGA, DSBGA. D flip flop is embedded in the Tape & Reel (TR) package. It is configured with Non-Invertedas an output. The trigger it is configured with uses Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates with an input voltage of 0.8V~2.7V volts. Currently, the operating temperature is -40°C~85°C TA. This D latch has the type D-Type. In FPGA terms, D flip flop is a type of 74AUCseries FPGA. A frequency of 275MHzshould not be exceeded by its output. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. It is a member of the 74AUC2G79 family. A voltage of 1.2V provides power to the D latch. A 2.5pFfarad input capacitance is provided by this T flip flop. A device of this type belongs to the family of AUC. It is mounted by the way of Surface Mount. There are 8pins on it. A Positive Edgeclock edge trigger is used in this device. This device has the base part number FF/Latches. 2 circuits are used to achieve its superior flexibility. Considering its reliability, this T flip flop is well suited for TR. In order to operate, the chip has 1 output lines. It consumes 10μA of quiescent current without being affected by external factors.
SN74AUC2G79YZPR Features
Tape & Reel (TR) package
74AUC series
8 pins
SN74AUC2G79YZPR Applications
There are a lot of Texas Instruments SN74AUC2G79YZPR Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Count Modes
- Circuit Design
- Control circuits
- QML qualified product
- Matched Rise and Fall
- Parallel data storage
- Consumer
- Buffered Clock
- Single Down Count-Control Line
