SN74AUC74RGYR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-VFQFN Exposed Pad |
| Number of Pins | 14 |
| Weight | 32.205058mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~2.7V |
| Terminal Position | QUAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Base Part Number | 74AUC74 |
| Function | Set(Preset) and Reset |
| Number of Outputs | 4 |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 2 |
| Output Current | 9mA |
| Clock Frequency | 350MHz |
| Propagation Delay | 12 ns |
| Quiescent Current | 10μA |
| Turn On Delay Time | 9.5 ns |
| Family | AUC |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Output High, Low | 9mA 9mA |
| Max I(ol) | 0.009 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 2.2ns @ 2.5V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| Number of Output Lines | 1 |
| fmax-Min | 350 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1mm |
| Length | 3.5mm |
| Width | 3.5mm |
| Thickness | 900μm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUC74RGYR Overview
It is embeded in 14-VFQFN Exposed Pad case. A package named Tape & Reel (TR)includes it. This output is configured with Differential. JK flip flop uses Positive Edgeas the trigger. It is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 0.8V~2.7V volts. Currently, the operating temperature is -40°C~85°C TA. It belongs to the type D-Typeof flip flops. In FPGA terms, D flip flop is a type of 74AUCseries FPGA. Its output frequency should not exceed 350MHz Hz. In 14terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. This D latch belongs to the family of 74AUC74. An input voltage of 1.2Vpowers the D latch. Input capacitance of this device is 2.5pF farads. This D flip flop belongs to the family of AUC. It is mounted by the way of Surface Mount. 14pins are included in its design. There is a clock edge trigger type of Positive Edgeon this device. This part is included in FF/Latches. A normal operating voltage (Vsup) should remain above 0.8V. Its flexibility is enhanced by 2 circuits. In view of its reliability, this D flip flop is a good fit for TR. With a current output of 9mA , it offers maximum design flexibility. In order for the chip to function, it has 1output lines. Quiescent current is consumed by the D latch in the amount of 10μA.
SN74AUC74RGYR Features
Tape & Reel (TR) package
74AUC series
14 pins
SN74AUC74RGYR Applications
There are a lot of Texas Instruments SN74AUC74RGYR Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- Balanced Propagation Delays
- ATE
- Data Synchronizers
- Safety Clamp
- Cold spare funcion
- Load Control
- Automotive
- Convert a momentary switch to a toggle switch
- Communications
