SN74AUP1G79DSFR
| Parameters | |
|---|---|
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.35mm |
| Base Part Number | 74AUP1G79 |
| Function | Standard |
| Number of Outputs | 1 |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Load Capacitance | 30pF |
| Number of Bits | 1 |
| Clock Frequency | 266MHz |
| Propagation Delay | 24 ns |
| Turn On Delay Time | 3 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 220000000Hz |
| Height | 400μm |
| Length | 1mm |
| Width | 1mm |
| Thickness | 350μm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
SN74AUP1G79DSFR Overview
It is packaged in the way of 6-XFDFN. The package Tape & Reel (TR)contains it. T flip flop uses Non-Invertedas the output. The trigger it is configured with uses Positive Edge. Surface Mountis occupied by this electronic component. A voltage of 0.8V~3.6Vis used as the supply voltage. Temperature is set to -40°C~85°C TA. This D latch has the type D-Type. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. A frequency of 266MHzshould not be exceeded by its output. T flip flop consumes 500nA quiescent energy. A total of 6 terminations have been made. The 74AUP1G79 family contains it. The power supply voltage is 1.2V. JK flip flop input capacitance is 1.5pF farads. The electronic device belongs to the AUP/ULP/Vfamily. There is an electronic part mounted in the way of Surface Mount. 6pins are included in its design. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. This RS flip flops is a part number FF/Latches. An electronic part designed with 1bits is used in this application. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 0.8V. On the basis of its reliable performance, this D flip flop is well suited for use with TR.
SN74AUP1G79DSFR Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
SN74AUP1G79DSFR Applications
There are a lot of Texas Instruments SN74AUP1G79DSFR Flip Flops applications.
- QML qualified product
- Set-reset capability
- ATE
- Memory
- Frequency Divider circuits
- Pattern generators
- Digital electronics systems
- Storage Registers
- EMI reduction circuitry
- Computing
