SN74AUP1G80DPWR
| Parameters | |
|---|---|
| Surface Mount | YES |
| Number of Pins | 5 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 5 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.2V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G80 |
| Function | Standard |
| Output Type | Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 260MHz |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 0.9μA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Propagation Delay (tpd) | 28.7 ns |
| Height | 0m |
| Length | 800μm |
| Width | 800μm |
| Thickness | 370μm |
| RoHS Status | ROHS3 Compliant |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Mounting Type | Surface Mount |
| Package / Case | 5-XFDFN Exposed Pad |
SN74AUP1G80DPWR Overview
The flip flop is packaged in 5-XFDFN Exposed Pad. The package Tape & Reel (TR)contains it. There is a Invertedoutput configured with it. The trigger it is configured with uses Positive Edge. Surface Mountis occupied by this electronic component. The JK flip flop operates at a voltage of 0.8V~3.6V. In this case, the operating temperature is -40°C~85°C TA. It is an electronic flip flop with the type D-Type. JK flip flop belongs to the 74AUPseries of FPGAs. A frequency of 260MHzshould be the maximum output frequency. The list contains 1 elements. During its operation, it consumes 0.9μA quiescent energy. There have been 5 terminations. If you search by 74AUP1G80, you will find similar parts. A voltage of 1.2V provides power to the D latch. The input capacitance of this JK flip flopis 1.5pF farads. AUP/ULP/Vis the family of this D flip flop. As you can see from the design, it has pins with 5. An electronic part with 1bits has been designed. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 0.8V.
SN74AUP1G80DPWR Features
Tape & Reel (TR) package
74AUP series
5 pins
1 Bits
SN74AUP1G80DPWR Applications
There are a lot of Texas Instruments SN74AUP1G80DPWR Flip Flops applications.
- Patented noise
- QML qualified product
- Pattern generators
- Shift registers
- Event Detectors
- Cold spare funcion
- Supports Live Insertion
- Control circuits
- Parallel data storage
- Latch
