SN74AUP1G80DSFR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.35mm |
| Base Part Number | 74AUP1G80 |
| Function | Standard |
| Number of Outputs | 1 |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Load Capacitance | 30pF |
| Output Current | 4mA |
| Number of Bits | 1 |
| Clock Frequency | 260MHz |
| Propagation Delay | 17.2 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 3.1 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 0.9μA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Prop. Delay@Nom-Sup | 28.7 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 400μm |
| Length | 1mm |
| Width | 1mm |
| Thickness | 350μm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP1G80DSFR Overview
6-XFDFNis the packaging method. It is contained within the Tape & Reel (TR)package. T flip flop uses Invertedas the output. This trigger is configured to use Positive Edge. Surface Mountis occupied by this electronic component. The JK flip flop operates at a voltage of 0.8V~3.6V. It is at -40°C~85°C TAdegrees Celsius that the system is operating. D-Typedescribes this flip flop. In this case, it is a type of FPGA belonging to the 74AUP series. Its output frequency should not exceed 260MHz Hz. Despite external influences, it consumes 0.9μAof quiescent current. Currently, there are 6 terminations. The 74AUP1G80 family contains this object. The power source is powered by 1.2V. This JK flip flop has a 1.5pFfarad input capacitance. An electronic device belonging to the family AUP/ULP/Vcan be found here. This electronic part is mounted in the way of Surface Mount. A total of 6pins are provided on this board. A Positive Edgeclock edge trigger is used in this device. The part is included in FF/Latches. The design is based on 1bits. Normally, the supply voltage (Vsup) should be kept above 0.8V. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. Featuring the maximum design flexibility, it has an output current of 4mA . Despite external influences, it consumes 500nAof quiescent current.
SN74AUP1G80DSFR Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
SN74AUP1G80DSFR Applications
There are a lot of Texas Instruments SN74AUP1G80DSFR Flip Flops applications.
- Common Clocks
- Convert a momentary switch to a toggle switch
- CMOS Process
- Load Control
- Buffered Clock
- Cold spare funcion
- Test & Measurement
- Supports Live Insertion
- Functionally equivalent to the MC10/100EL29
- ESD protection
