SN74AUP2G79DQER
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.35mm |
| Base Part Number | 74AUP2G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 30pF |
| Clock Frequency | 266MHz |
| Propagation Delay | 24 ns |
| Turn On Delay Time | 3 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Number of Gates | 2 |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.3ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 400μm |
| Length | 1.4mm |
| Width | 1mm |
| Thickness | 370μm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP2G79DQER Overview
8-XFDFNis the way it is packaged. As part of the package Tape & Reel (TR), it is embedded. In the configuration, Non-Invertedis used as the output. This trigger uses the value Positive Edge. It is mounted in the way of Surface Mount. It operates with a supply voltage of 0.8V~3.6V. Currently, the operating temperature is -40°C~85°C TA. The type of this D latch is D-Type. It is a type of FPGA belonging to the 74AUP series. A frequency of 266MHzshould not be exceeded by its output. There is a consumption of 500nAof quiescent energy. There have been 8 terminations. JK flip flop belongs to 74AUP2G79 family. The power supply voltage is 1.2V. Its input capacitance is 1.5pF farads. In terms of electronic devices, this device belongs to the AUP/ULP/Vfamily of devices. There is an electronic part mounted in the way of Surface Mount. As you can see from the design, it has pins with 8. Its clock edge trigger type is Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. 3.6Vis the maximum supply voltage (Vsup). As a result of its reliability, this D flip flop is ideally suited for TR. A basic building block consists of 2 gates.
SN74AUP2G79DQER Features
Tape & Reel (TR) package
74AUP series
8 pins
2 gates
SN74AUP2G79DQER Applications
There are a lot of Texas Instruments SN74AUP2G79DQER Flip Flops applications.
- CMOS Process
- Safety Clamp
- Matched Rise and Fall
- Latch
- Control circuits
- Computers
- Synchronous counter
- Event Detectors
- Single Up Count-Control Line
- Memory
