SN74AUP2G80DQER
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 6 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.35mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP2G80 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 30pF |
| Clock Frequency | 257MHz |
| Propagation Delay | 6.4 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 3.1 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Number of Gates | 2 |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 400μm |
| Length | 1.4mm |
| Width | 1mm |
| Thickness | 370μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP2G80DQER Overview
It is packaged in the way of 8-XFDFN. D flip flop is embedded in the Tape & Reel (TR) package. T flip flop uses Invertedas the output. This trigger is configured to use Positive Edge. The electronic part is mounted in the way of Surface Mount. A supply voltage of 0.8V~3.6V is required for operation. It is at -40°C~85°C TAdegrees Celsius that the system is operating. Logic flip flops of this type are classified as D-Type. This type of FPGA is a part of the 74AUP series. You should not exceed 257MHzin its output frequency. A total of 8terminations have been recorded. D latch belongs to the 74AUP2G80 family. A voltage of 1.2V provides power to the D latch. A 1.5pFfarad input capacitance is provided by this T flip flop. It is a member of the AUP/ULP/Vfamily of D flip flop. In this case, the electronic component is mounted in the way of Surface Mount. This board has 8 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. It is included in FF/Latches. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. This D flip flop is well suited for TR based on its reliable performance. Despite external influences, it consumes 500nAof quiescent current. There are 2 gates in its basic building block.
SN74AUP2G80DQER Features
Tape & Reel (TR) package
74AUP series
8 pins
2 gates
SN74AUP2G80DQER Applications
There are a lot of Texas Instruments SN74AUP2G80DQER Flip Flops applications.
- Registers
- Modulo – n – counter
- Frequency Dividers
- Guaranteed simultaneous switching noise level
- Buffer registers
- Individual Asynchronous Resets
- Computing
- Test & Measurement
- Clock pulse
- Shift Registers
