SN74AUP2G80RSER
| Parameters | |
|---|---|
| Turn On Delay Time | 3.1 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Number of Gates | 2 |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 600μm |
| Length | 1.5mm |
| Width | 1.5mm |
| Thickness | 550μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 6 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-UFQFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP2G80 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 30pF |
| Clock Frequency | 257MHz |
| Propagation Delay | 4.3 ns |
SN74AUP2G80RSER Overview
The flip flop is packaged in 8-UFQFN. The Tape & Reel (TR)package contains it. There is a Invertedoutput configured with it. There is a trigger configured with Positive Edge. Surface Mountis in the way of this electric part. A 0.8V~3.6Vsupply voltage is required for it to operate. The operating temperature is -40°C~85°C TA. It belongs to the type D-Typeof flip flops. It belongs to the 74AUPseries of FPGAs. Its output frequency should not exceed 257MHz Hz. This process consumes 500nA quiescents. 8terminations have occurred. The 74AUP2G80 family contains it. A voltage of 1.2V is used to power it. Its input capacitance is 1.5pF farads. In this case, the D flip flop belongs to the AUP/ULP/Vfamily. The electronic part is mounted in the way of Surface Mount. 8pins are included in its design. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. It is part of the FF/Latchesbase part number family. Vsup reaches its maximum value at 3.6V. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. 2 gates constitute its basic building block.
SN74AUP2G80RSER Features
Tape & Reel (TR) package
74AUP series
8 pins
2 gates
SN74AUP2G80RSER Applications
There are a lot of Texas Instruments SN74AUP2G80RSER Flip Flops applications.
- Data storage
- Buffer registers
- 2 – Bit synchronous counter
- Storage Registers
- Cold spare funcion
- ATE
- ESD protection
- Automotive
- Communications
- Single Up Count-Control Line
