SN74F112D
| Parameters | |
|---|---|
| Family | F/FAST |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Quiescent (Iq) | 19mA |
| Current - Output High, Low | 1mA 20mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Schmitt Trigger | No |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74F |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Base Part Number | 74F112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Power Supplies | 5V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 20mA |
| Clock Frequency | 130MHz |
| Propagation Delay | 7.5 ns |
| Turn On Delay Time | 4.6 ns |
SN74F112D Overview
The flip flop is packaged in 16-SOIC (0.154, 3.90mm Width). The Tubepackage contains it. T flip flop uses Differentialas its output configuration. In the configuration of the trigger, Negative Edgeis used. This electronic part is mounted in the way of Surface Mount. A 4.5V~5.5Vsupply voltage is required for it to operate. Temperature is set to 0°C~70°C TA. JK Typeis the type of this D latch. The 74Fseries comprises this type of FPGA. A frequency of 130MHzshould be the maximum output frequency. There is a consumption of 19mAof quiescent energy. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74F112family includes it. An input voltage of 5Vpowers the D latch. It is a member of the F/FASTfamily of D flip flop. It is mounted by the way of Surface Mount. 16pins are included in its design. It has a clock edge trigger type of Negative Edge. This part is included in FF/Latches. The superior flexibility of this product is achieved by using 2 circuits. A total of 5V power supplies are needed to run it. The supply voltage should be maintained at 5V for high efficiency. The 20mA output current allows it to be designed with the greatest amount of flexibility.
SN74F112D Features
Tube package
74F series
16 pins
5V power supplies
SN74F112D Applications
There are a lot of Texas Instruments SN74F112D Flip Flops applications.
- Reduced system switching noise
- Data storage
- Buffer registers
- Synchronous counter
- Instrumentation
- Memory
- Test & Measurement
- Circuit Design
- Count Modes
- CMOS Process
