SN74F280BN3
| Parameters | |
|---|---|
| Package / Case | PDIP |
| Surface Mount | NO |
| Number of Pins | 14 |
| Pbfree Code | no |
| Number of Terminations | 14 |
| Technology | TTL |
| Terminal Position | DUAL |
| Terminal Form | THROUGH-HOLE |
| Number of Functions | 1 |
| Supply Voltage | 5V |
| Pin Count | 14 |
| Number of Outputs | 9 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 5.5V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Bits | 2 |
| Propagation Delay | 11 ns |
| Family | F/FAST |
| Output Polarity | COMPLEMENTARY |
| Logic IC Type | PARITY GENERATOR/CHECKER |
| Height Seated (Max) | 5.08mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
SN74F280BN3 Overview
This device is packaged in a PDIP package. 14 terminations are used for its configuration. By supplying 5Vwith a voltage of 5V , the device can be operated in a completely flexible manner. There are 14pins on all components. In the circuit, 14pins are used to connect other components. It is included in the F/FASTfamily. The are 2 bits information in the device. Pbfree code may produce the result no. The device is manufactured at COMMERCIALdegrees Celsius. A voltage of 4.5V is the minimum supply voltage (Vsup). It is possible to provide a voltage up to 5.5V (Vsup). In this case, PARITY GENERATOR/CHECKERrefers to the logic IC type being used. A temperature of 70°Cis usually set as the maximum operating temperature. 9 outputs is sent by the system.
SN74F280BN3 Features
Embedded in the PDIP package
PARITY GENERATOR/CHECKER as logic IC type
SN74F280BN3 Applications
There are a lot of Texas Instruments SN74F280BN3 Counters & Dividers applications.
- Fixed and programmable counters greater than 10
- Counter control/timers
- Communications Digital Frequency Synthesizers;
- Time Out Timer for Consumer-Application Industrial Controls
- Frequency division
- Fixed or Programmable Frequency Division
- SQUARE ROOT
- LINEARIZATION
- ANALOG SIGNAL PROCESSING
- Fixed and programmable divide-by-10,9,8,7,6,5,4,3,2 counters
