SN74HC112DR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74HC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 13 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 13 ns |
| Family | HC/UH |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.004 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 21ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 3pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Number of Output Lines | 3 |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74HC112DR Overview
16-SOIC (0.154, 3.90mm Width)is the packaging method. There is an embedded version in the package Cut Tape (CT). The output it is configured with uses Differential. This trigger is configured to use Negative Edge. Surface Mountis positioned in the way of this electronic part. With a supply voltage of 2V~6V volts, it operates. The operating temperature is -40°C~85°C TA. A flip flop of this type is classified as a JK Type. In FPGA terms, D flip flop is a type of 74HCseries FPGA. It should not exceed 60MHzin terms of its output frequency. A total of 16terminations have been recorded. JK flip flop belongs to 74HC112 family. Power is provided by a 5V supply. Its input capacitance is 3pF farads. It is a member of the HC/UHfamily of D flip flop. This electronic part is mounted in the way of Surface Mount. The 16pins are designed into the board. The clock edge trigger type for this device is Negative Edge. This part is included in FF/Latches. It reaches 6Vwhen the supply voltage is maximal (Vsup). If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 2V. Its superior flexibility is attributed to its use of 2 circuits. This D flip flop is well suited for TR based on its reliable performance. A high level of efficiency can be achieved by maintaining the supply voltage at 5V. The output current of 5.2mA makes it feature maximum design flexibility. There are 3 output lines in this JK flip flop. There is 4μA quiescent current consumption by it.
SN74HC112DR Features
Cut Tape (CT) package
74HC series
16 pins
SN74HC112DR Applications
There are a lot of Texas Instruments SN74HC112DR Flip Flops applications.
- Control circuits
- Patented noise
- Clock pulse
- Bus hold
- Set-reset capability
- Single Down Count-Control Line
- Data storage
- Count Modes
- Individual Asynchronous Resets
- Shift registers
