SN74LS112ADR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LS |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | TTL |
| Voltage - Supply | 4.75V~5.25V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Base Part Number | 74LS112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Power Supplies | 5V |
| Number of Circuits | 2 |
| Output Current | 8mA |
| Clock Frequency | 45MHz |
| Propagation Delay | 20 ns |
| Quiescent Current | 6mA |
| Turn On Delay Time | 15 ns |
| Family | LS |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 400μA 8mA |
| Max I(ol) | 0.008 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 20ns @ 5V, 15pF |
| Trigger Type | Negative Edge |
| Schmitt Trigger | No |
| Number of Input Lines | 5 |
| Clock Edge Trigger Type | Negative Edge |
| Max Frequency@Nom-Sup | 30000000Hz |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LS112ADR Overview
As a result, it is packaged as 16-SOIC (0.154, 3.90mm Width). There is an embedded version in the package Tape & Reel (TR). There is a Differentialoutput configured with it. Negative Edgeis the trigger it is configured with. Surface Mountmounts this electrical part. The JK flip flop operates at 4.75V~5.25Vvolts. 0°C~70°C TAis the operating temperature. JK Typedescribes this flip flop. It is a type of FPGA belonging to the 74LS series. A frequency of 45MHzshould not be exceeded by its output. There have been 16 terminations. If you search by 74LS112, you will find similar parts. The D flip flop is powered by a voltage of 5V . This D flip flop belongs to the family of LS. The electronic part is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 16. This device exhibits a clock edge trigger type of Negative Edge. There is a base part number FF/Latchesfor the RS flip flops. To achieve this superior flexibility, 2 circuits are used. This D flip flop is well suited for TR based on its reliable performance. The power supply is 5V. It is recommended that the supply voltage be kept at 5Vto maximize efficiency. Featuring the maximum design flexibility, it has an output current of 8mA . Currently, there are 5 lines of input. As a result, it consumes 6mA of quiescent current without being affected by external factors.
SN74LS112ADR Features
Tape & Reel (TR) package
74LS series
16 pins
5V power supplies
SN74LS112ADR Applications
There are a lot of Texas Instruments SN74LS112ADR Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- Circuit Design
- Reduced system switching noise
- Synchronous counter
- Parallel data storage
- Test & Measurement
- Frequency Divider circuits
- Dynamic threshold performance
- Bounce elimination switch
- ESD protection
