Parameters |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
16-SSOP (0.209, 5.30mm Width) |
Number of Pins |
16 |
Weight |
128.593437mg |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tape & Reel (TR) |
Series |
74LV |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
16 |
Type |
D-Type |
Subcategory |
FF/Latches |
Packing Method |
TAPE AND REEL |
Technology |
CMOS |
Voltage - Supply |
2V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Supply Voltage |
2.5V |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Base Part Number |
74LV174 |
Function |
Master Reset |
Qualification Status |
Not Qualified |
Output Type |
Non-Inverted |
Number of Elements |
1 |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
5.5V |
Power Supplies |
3.3V |
Supply Voltage-Min (Vsup) |
2V |
Number of Circuits |
7 |
Load Capacitance |
50pF |
Output Current |
12mA |
Clock Frequency |
180MHz |
Propagation Delay |
20.6 ns |
Turn On Delay Time |
3 ns |
Family |
LV/LV-A/LVX/H |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
20μA |
Current - Output High, Low |
12mA 12mA |
Number of Bits per Element |
6 |
Max Propagation Delay @ V, Max CL |
9.2ns @ 5V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
1.7pF |
Number of Input Lines |
2 |
Clock Edge Trigger Type |
Positive Edge |
Max Frequency@Nom-Sup |
50000000Hz |
Width |
5.3mm |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
SN74LV174ADBRE4 Overview
As a result, it is packaged as 16-SSOP (0.209, 5.30mm Width). There is an embedded version in the package Tape & Reel (TR). This output is configured with Non-Inverted. It is configured with a trigger that uses Positive Edge. This electronic part is mounted in the way of Surface Mount. The JK flip flop operates at 2V~5.5Vvolts. A temperature of -40°C~85°C TAis considered to be the operating temperature. This D latch has the type D-Type. The 74LVseries comprises this type of FPGA. This D flip flop should not have a frequency greater than 180MHz. The element count is 1 . Despite external influences, it consumes 20μAof quiescent current. The number of terminations is 16. It is a member of the 74LV174 family. A voltage of 2.5V is used to power it. The input capacitance of this JK flip flopis 1.7pF farads. This D flip flop belongs to the family of LV/LV-A/LVX/H. It is mounted by the way of Surface Mount. 16pins are included in its design. The clock edge trigger type for this device is Positive Edge. It is part of the FF/Latchesbase part number family. The maximal supply voltage (Vsup) reaches 5.5V. Normally, the supply voltage (Vsup) should be above 2V. The superior flexibility is achieved through the use of 7 circuits. In view of its reliability, this D flip flop is a good fit for TAPE AND REEL. The D latch runs on a voltage of 3.3V volts. The output current of 12mA makes it feature maximum design flexibility. 2input lines are available for you to choose from.
SN74LV174ADBRE4 Features
Tape & Reel (TR) package
74LV series
16 pins
3.3V power supplies
SN74LV174ADBRE4 Applications
There are a lot of Texas Instruments SN74LV174ADBRE4 Flip Flops applications.
- Buffer registers
- Parallel data storage
- Memory
- Set-reset capability
- Registers
- Frequency Dividers
- Differential Individual
- Storage Registers
- Bounce elimination switch
- Communications