SN74LV273ADWG4
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Number of Pins | 20 |
| Weight | 500.709277mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.5V |
| Base Part Number | 74LV273 |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Output Current | 12mA |
| Number of Bits | 8 |
| Clock Frequency | 160MHz |
| Propagation Delay | 22.1 ns |
| Turn On Delay Time | 4.8 ns |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Max Propagation Delay @ V, Max CL | 11ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2pF |
| Power Supply Current-Max (ICC) | 0.02mA |
| Number of Input Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 45000000Hz |
| Height | 2.65mm |
| Length | 12.8mm |
| Width | 7.5mm |
| Thickness | 2.35mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LV273ADWG4 Overview
As a result, it is packaged as 20-SOIC (0.295, 7.50mm Width). There is an embedded version in the package Tube. Non-Invertedis the output configured for it. This trigger uses the value Positive Edge. The electronic part is mounted in the way of Surface Mount. A supply voltage of 2V~5.5V is required for operation. It is operating at a temperature of -40°C~125°C TA. This D latch has the type D-Type. The FPGA belongs to the 74LV series. Its output frequency should not exceed 160MHz. D latch consists of 1 elements. As a result, it consumes 20μA of quiescent current without being affected by external factors. A total of 20 terminations have been made. JK flip flop belongs to 74LV273 family. The D flip flop is powered by a voltage of 2.5V . JK flip flop input capacitance is 2pF farads. Devices in the LV/LV-A/LVX/Hfamily are electronic devices. Surface Mount mounts this electronic component. 20pins are included in its design. In this device, the clock edge trigger type is Positive Edge. This device is part of the FF/Latchesbase part number family. An electronic part with 8bits has been designed. Vsup reaches 5.5V, the maximal supply voltage. A normal operating voltage (Vsup) should remain above 2V. The power supply is 3.3V. This T flip flop features a maximum design flexibility due to its output current of 12mA. It has 8lines.
SN74LV273ADWG4 Features
Tube package
74LV series
20 pins
8 Bits
3.3V power supplies
SN74LV273ADWG4 Applications
There are a lot of Texas Instruments SN74LV273ADWG4 Flip Flops applications.
- Buffered Clock
- Control circuits
- Matched Rise and Fall
- Safety Clamp
- Asynchronous counter
- Registers
- Counters
- Frequency Dividers
- Data storage
- ESD performance
