SN74LV273ANS
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LV273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Clock Frequency | 160MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 11ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2pF |
| Propagation Delay (tpd) | 25 ns |
| Max Frequency@Nom-Sup | 45000000Hz |
| Height Seated (Max) | 2mm |
| Width | 5.3mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
SN74LV273ANS Overview
The item is packaged in 20-SOIC (0.209, 5.30mm Width)cases. The Tubepackage contains it. In the configuration, Non-Invertedis used as the output. The trigger configured with it uses Positive Edge. Surface Mountis in the way of this electric part. A voltage of 2V~5.5Vis required for its operation. The operating temperature is -40°C~125°C TA. It belongs to the type D-Typeof flip flops. This type of FPGA is a part of the 74LV series. There should be no greater frequency than 160MHzon its output. In total, it contains 1 elements. It consumes 20μA of quiescent 20terminations have occurred. JK flip flop belongs to 74LV273 family. A voltage of 2.5V provides power to the D latch. Its input capacitance is 2pFfarads. LV/LV-A/LVX/His the family of this D flip flop. There is a base part number FF/Latchesfor the RS flip flops. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. It is imperative that the supply voltage (Vsup) is maintained above 2Vin order to ensure normal operation. In order for the device to operate, it requires 3.3V power supplies.
SN74LV273ANS Features
Tube package
74LV series
3.3V power supplies
SN74LV273ANS Applications
There are a lot of Texas Instruments SN74LV273ANS Flip Flops applications.
- Individual Asynchronous Resets
- Functionally equivalent to the MC10/100EL29
- 2 – Bit synchronous counter
- Pattern generators
- Common Clocks
- Single Up Count-Control Line
- Balanced 24 mA output drivers
- Circuit Design
- Reduced system switching noise
- ESCC
