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SN74LV374ATRGYR

4.5V~5.5V 150MHz 8 Bit D-Type Flip Flop QUAD 74LV374 20 Pins 2μA 74LV Series 20-VFQFN Exposed Pad


  • Manufacturer: Texas Instruments
  • Nocochips NO: 815-SN74LV374ATRGYR
  • Package: 20-VFQFN Exposed Pad
  • Datasheet: -
  • Stock: 731
  • Description: 4.5V~5.5V 150MHz 8 Bit D-Type Flip Flop QUAD 74LV374 20 Pins 2μA 74LV Series 20-VFQFN Exposed Pad(Kg)

Details

Tags

Parameters
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 20-VFQFN Exposed Pad
Number of Pins 20
Weight 43.006227mg
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Series 74LV
JESD-609 Code e4
Pbfree Code yes
Part Status Obsolete
Moisture Sensitivity Level (MSL) 2 (1 Year)
Number of Terminations 20
Type D-Type
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory FF/Latches
Packing Method TAPE AND REEL
Technology CMOS
Voltage - Supply 4.5V~5.5V
Terminal Position QUAD
Peak Reflow Temperature (Cel) 260
Supply Voltage 2.5V
Terminal Pitch 0.5mm
Base Part Number 74LV374
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 1
Polarity Non-Inverting
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 2V
Number of Circuits 8
Load Capacitance 50pF
Number of Ports 2
Output Current 16mA
Number of Bits 8
Clock Frequency 150MHz
Propagation Delay 19.3 ns
Turn On Delay Time 4.9 ns
Family LV/LV-A/LVX/H
Logic Function D-Type, Flip-Flop
Current - Quiescent (Iq) 2μA
Output Characteristics 3-STATE
Current - Output High, Low 16mA 16mA
Max Propagation Delay @ V, Max CL 10.1ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4pF
Number of Input Lines 2
Clock Edge Trigger Type Positive Edge
Max Frequency@Nom-Sup 50000000Hz
Length 4.5mm
Width 3.5mm
Radiation Hardening No
RoHS Status ROHS3 Compliant
Lead Free Contains Lead

SN74LV374ATRGYR Overview


The flip flop is packaged in a case of 20-VFQFN Exposed Pad. It is included in the package Tape & Reel (TR). There is a Tri-State, Non-Invertedoutput configured with it. The trigger it is configured with uses Positive Edge. It is mounted in the way of Surface Mount. The supply voltage is set to 4.5V~5.5V. In the operating environment, the temperature is -40°C~125°C TA. This electronic flip flop is of type D-Type. FPGAs belonging to the 74LVseries contain this type of chip. This D flip flop should not have a frequency greater than 150MHz. D latch consists of 1 elements. There is a consumption of 2μAof quiescent energy. Terminations are 20. The object belongs to the 74LV374 family. The D flip flop is powered by a voltage of 2.5V . The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. A device of this type belongs to the family of LV/LV-A/LVX/H. Surface Mount mounts this electronic component. This board has 20 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. The design is based on 8bits. Vsup reaches its maximum value at 5.5V. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 2V. The superior flexibility of this product is achieved by using 8 circuits. As a result of its reliable performance, this T flip flop is suitable for TAPE AND REEL. There are 3.3V power supplies attached to it. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This T flip flop features a maximum design flexibility due to its output current of 16mA. A total of 2input lines have been provided.

SN74LV374ATRGYR Features


Tape & Reel (TR) package
74LV series
20 pins
8 Bits
3.3V power supplies

SN74LV374ATRGYR Applications


There are a lot of Texas Instruments SN74LV374ATRGYR Flip Flops applications.

  • Consumer
  • Buffer registers
  • Computers
  • Safety Clamp
  • Cold spare funcion
  • Counters
  • Synchronous counter
  • Guaranteed simultaneous switching noise level
  • Individual Asynchronous Resets
  • Common Clocks

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