SN74LV74APW
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 14 |
| Weight | 57.209338mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.5V |
| Base Part Number | 74LV74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 12mA |
| Clock Frequency | 140MHz |
| Propagation Delay | 17.5 ns |
| Turn On Delay Time | 9.8 ns |
| Family | LV/LV-A/LVX/H |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 9.3ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2pF |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 45000000Hz |
| Height | 1.2mm |
| Length | 5mm |
| Width | 4.4mm |
| Thickness | 1mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LV74APW Overview
The item is packaged in 14-TSSOP (0.173, 4.40mm Width)cases. D flip flop is embedded in the Tube package. It is configured with Differentialas an output. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Surface Mount. Powered by a 2V~5.5Vvolt supply, it operates as follows. It is operating at -40°C~125°C TA. Logic flip flops of this type are classified as D-Type. In FPGA terms, D flip flop is a type of 74LVseries FPGA. Its output frequency should not exceed 140MHz Hz. This process consumes 20μA quiescents. A total of 14terminations have been recorded. If you search by 74LV74, you will find similar parts. Power is supplied from a voltage of 2.5V volts. Input capacitance of this device is 2pF farads. Electronic devices of this type belong to the LV/LV-A/LVX/Hfamily. The electronic part is mounted in the way of Surface Mount. There are 14pins on it. Its clock edge trigger type is Positive Edge. This RS flip flops is a part number FF/Latches. Vsup reaches its maximum value at 5.5V. A normal operating voltage (Vsup) should remain above 2V. Using 2 circuits, it is highly flexible. The power supply is 3.3V. With an output current of 12mA, this device offers maximum design flexibility.
SN74LV74APW Features
Tube package
74LV series
14 pins
3.3V power supplies
SN74LV74APW Applications
There are a lot of Texas Instruments SN74LV74APW Flip Flops applications.
- Data Synchronizers
- EMI reduction circuitry
- Individual Asynchronous Resets
- Pattern generators
- Control circuits
- Frequency Divider circuits
- Synchronous counter
- Frequency division
- Circuit Design
- Shift registers
