SN74LVC112AD
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Base Part Number | 74LVC112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 150MHz |
| Propagation Delay | 7.1 ns |
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.9ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.8 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 4.5pF |
| Schmitt Trigger | No |
| Number of Input Lines | 3 |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVC112AD Overview
The item is packaged in 16-SOIC (0.154, 3.90mm Width)cases. Package Tubeembeds it. The output it is configured with uses Differential. It is configured with a trigger that uses a value of Negative Edge. There is an electronic component mounted in the way of Surface Mount. With a supply voltage of 1.65V~3.6V volts, it operates. It is operating at -40°C~85°C TA. This electronic flip flop is of type JK Type. In FPGA terms, D flip flop is a type of 74LVCseries FPGA. There should be no greater frequency than 150MHzon its output. It consumes 10μA of quiescent In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. It is a member of the 74LVC112 family. A voltage of 1.8V is used to power it. This T flip flop has a capacitance of 4.5pF farads at the input. Devices in the LVC/LCX/Zfamily are electronic devices. In this case, the electronic component is mounted in the way of Surface Mount. A total of 16pins are provided on this board. This device has the clock edge trigger type of Negative Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. Normally, the supply voltage (Vsup) should be above 2V. The superior flexibility of this circuit is achieved by using 2 circuits. The 24mA output current allows it to be designed with the greatest amount of flexibility. Currently, there are 3 input lines present.
SN74LVC112AD Features
Tube package
74LVC series
16 pins
SN74LVC112AD Applications
There are a lot of Texas Instruments SN74LVC112AD Flip Flops applications.
- Latch-up performance
- Memory
- Differential Individual
- Counters
- Cold spare funcion
- Event Detectors
- Synchronous counter
- Clock pulse
- ATE
- High Performance Logic for test systems
