SN74LVC112ADGVRG4
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-TFSOP (0.173, 4.40mm Width) |
| Number of Pins | 16 |
| Weight | 41.900595mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.4mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVC112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 150MHz |
| Propagation Delay | 7.1 ns |
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, JK-Type |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.9ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.8 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 4.5pF |
| Schmitt Trigger | No |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.2mm |
| Length | 3.6mm |
| Width | 4.4mm |
| Thickness | 1.05mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVC112ADGVRG4 Overview
The flip flop is packaged in 16-TFSOP (0.173, 4.40mm Width). As part of the package Tape & Reel (TR), it is embedded. In the configuration, Differentialis used as the output. The trigger configured with it uses Negative Edge. The electronic part is mounted in the way of Surface Mount. A voltage of 1.65V~3.6Vis required for its operation. It is operating at a temperature of -40°C~85°C TA. The type of this D latch is JK Type. The 74LVCseries comprises this type of FPGA. It should not exceed 150MHzin its output frequency. T flip flop consumes 10μA quiescent energy. A total of 16terminations have been recorded. You can search similar parts based on 74LVC112. Power is supplied from a voltage of 1.8V volts. This JK flip flop has a 4.5pFfarad input capacitance. LVC/LCX/Zis the family of this D flip flop. Surface Mount mounts this electronic component. There are 16pins on it. Its clock edge trigger type is Negative Edge. It is included in FF/Latches. Vsup reaches 3.6V, the maximal supply voltage. A normal operating voltage (Vsup) should remain above 2V. Its flexibility is enhanced by 2 circuits. Considering the reliability of this T flip flop, it is well suited for TR. The system runs on a power supply of 3.3V watts. The output current of 24mA makes it feature maximum design flexibility.
SN74LVC112ADGVRG4 Features
Tape & Reel (TR) package
74LVC series
16 pins
3.3V power supplies
SN74LVC112ADGVRG4 Applications
There are a lot of Texas Instruments SN74LVC112ADGVRG4 Flip Flops applications.
- Buffer registers
- Cold spare funcion
- QML qualified product
- Synchronous counter
- CMOS Process
- Individual Asynchronous Resets
- Control circuits
- Clock pulse
- Load Control
- Memory
