Parameters |
Factory Lead Time |
1 Week |
Lifecycle Status |
ACTIVE (Last Updated: 4 days ago) |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
48-BSSOP (0.295, 7.50mm Width) |
Number of Pins |
48 |
Weight |
600.301152mg |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Cut Tape (CT) |
Series |
74LVC |
JESD-609 Code |
e4 |
Pbfree Code |
yes |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
48 |
ECCN Code |
EAR99 |
Type |
D-Type |
Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au) |
Subcategory |
FF/Latches |
Packing Method |
TR |
Technology |
CMOS |
Voltage - Supply |
1.65V~3.6V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
1.8V |
Terminal Pitch |
0.635mm |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Base Part Number |
74LVC16374 |
Function |
Standard |
Qualification Status |
Not Qualified |
Output Type |
Tri-State, Non-Inverted |
Number of Elements |
2 |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
3.6V |
Power Supplies |
3.3V |
Load Capacitance |
50pF |
Number of Ports |
2 |
Output Current |
24mA |
Number of Bits |
16 |
Clock Frequency |
150MHz |
Propagation Delay |
4.9 ns |
Turn On Delay Time |
1.5 ns |
Family |
LVC/LCX/Z |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
20μA |
Output Characteristics |
3-STATE |
Current - Output High, Low |
24mA 24mA |
Number of Bits per Element |
8 |
Max Propagation Delay @ V, Max CL |
4.5ns @ 3.3V, 50pF |
Prop. Delay@Nom-Sup |
4.5 ns |
Trigger Type |
Positive Edge |
Input Capacitance |
5pF |
Number of Output Lines |
1 |
Count Direction |
UNIDIRECTIONAL |
Clock Edge Trigger Type |
Positive Edge |
Translation |
N/A |
Height |
2.79mm |
Length |
15.88mm |
Width |
7.49mm |
Thickness |
2.59mm |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
SN74LVC16374ADLR Overview
48-BSSOP (0.295, 7.50mm Width)is the way it is packaged. You can find it in the Cut Tape (CT)package. This output is configured with Tri-State, Non-Inverted. Positive Edgeis the trigger it is configured with. It is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 1.65V~3.6V. It is at -40°C~85°C TAdegrees Celsius that the system is operating. D-Typedescribes this flip flop. The 74LVCseries comprises this type of FPGA. Its output frequency should not exceed 150MHz Hz. The list contains 2 elements. T flip flop consumes 20μA quiescent energy. A total of 48 terminations have been made. This D latch belongs to the family of 74LVC16374. It is powered from a supply voltage of 1.8V. A JK flip flop with a 5pFfarad input capacitance is used here. The electronic device belongs to the LVC/LCX/Zfamily. This electronic part is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 48. It has a clock edge trigger type of Positive Edge. It is included in FF/Latches. The design is based on 16bits. It reaches 3.6Vwhen the supply voltage is maximal (Vsup). In light of its reliable performance, this T flip flop is well suited for TR. The D latch operates on 3.3V volts. A D flip flop with 2embedded ports is available. This T flip flop features a maximum design flexibility due to its output current of 24mA. There are 1 output Lines, which generate the binary equivalent of the input line whose value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or “B. C. D” (binary coded decimal) output code.
SN74LVC16374ADLR Features
Cut Tape (CT) package
74LVC series
48 pins
16 Bits
3.3V power supplies
SN74LVC16374ADLR Applications
There are a lot of Texas Instruments SN74LVC16374ADLR Flip Flops applications.
- Power down protection
- Balanced 24 mA output drivers
- Data transfer
- Automotive
- Registers
- Data storage
- Single Down Count-Control Line
- Digital electronics systems
- Clock pulse
- 2 – Bit synchronous counter