SN74LVC16374AZQLR
| Parameters | |
|---|---|
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Output Current | 24mA |
| Number of Bits | 16 |
| Clock Frequency | 150MHz |
| Propagation Delay | 4.9 ns |
| Turn On Delay Time | 1.5 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 20μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 1 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Height | 1mm |
| Length | 7mm |
| Width | 4.5mm |
| Thickness | 750μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Lifecycle Status | LIFEBUY (Last Updated: 2 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 56-VFBGA |
| Number of Pins | 56 |
| Weight | 58.28662mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Last Time Buy |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVC16374 |
| Function | Standard |
SN74LVC16374AZQLR Overview
The package is in the form of 56-VFBGA. D flip flop is embedded in the Tape & Reel (TR) package. As configured, the output uses Tri-State, Non-Inverted. It is configured with a trigger that uses Positive Edge. There is an electric part mounted in the way of Surface Mount. A supply voltage of 1.65V~3.6V is required for operation. A temperature of -40°C~85°C TAis used in the operation. D-Typedescribes this flip flop. JK flip flop belongs to the 74LVCseries of FPGAs. This D flip flop should not have a frequency greater than 150MHz. The element count is 2 . T flip flop consumes 20μA quiescent energy. A total of 56 terminations have been made. D latch belongs to the 74LVC16374 family. The power source is powered by 1.8V. This T flip flop has a capacitance of 5pF farads at the input. It is a member of the LVC/LCX/Zfamily of D flip flop. There is an electronic component mounted in the way of Surface Mount. A total of 56pins are provided on this board. This device has Positive Edgeas its clock edge trigger type. There is a FF/Latchesbase part number assigned to the RS flip flops. An electronic part with 16bits has been designed. As soon as 3.6Vis reached, Vsup reaches its maximum value. Due to its reliability, this T flip flop is well suited for TR. It operates from 3.3V power supplies. This flip flop has a total of 2ports. Its output current of 24mAallows for maximum design flexibility. There are 1 input Lines, which consist of an electronic circuit connected between the ac mains and the rectifier input stage of the switching power supply.
SN74LVC16374AZQLR Features
Tape & Reel (TR) package
74LVC series
56 pins
16 Bits
3.3V power supplies
SN74LVC16374AZQLR Applications
There are a lot of Texas Instruments SN74LVC16374AZQLR Flip Flops applications.
- 2 – Bit synchronous counter
- ESD performance
- Balanced 24 mA output drivers
- Latch
- Buffer registers
- Set-reset capability
- Communications
- ATE
- Digital electronics systems
- Shift Registers
