SN74LVC1G175DBVR
| Parameters | |
|---|---|
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 32mA |
| Max I(ol) | 0.032 A |
| Max Propagation Delay @ V, Max CL | 5ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 5.7 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1.45mm |
| Length | 2.9mm |
| Width | 1.6mm |
| Thickness | 1.2mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | SOT-23-6 |
| Number of Pins | 6 |
| Weight | 6.492041mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.95mm |
| Base Part Number | 74LVC1G175 |
| Function | Reset |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Number of Circuits | 1 |
| Load Capacitance | 50pF |
| Output Current | 32mA |
| Number of Bits | 1 |
| Clock Frequency | 175MHz |
| Propagation Delay | 13.4 ns |
| Quiescent Current | 10μA |
SN74LVC1G175DBVR Overview
The package is in the form of SOT-23-6. Package Tape & Reel (TR)embeds it. As configured, the output uses Non-Inverted. This trigger is configured to use Positive Edge. This electronic part is mounted in the way of Surface Mount. A 1.65V~5.5Vsupply voltage is required for it to operate. It is operating at a temperature of -40°C~125°C TA. The type of this D latch is D-Type. The 74LVCseries comprises this type of FPGA. You should not exceed 175MHzin the output frequency of the device. The number of terminations is 6. The 74LVC1G175 family contains this object. Power is supplied from a voltage of 1.8V volts. JK flip flop input capacitance is 3pF farads. Electronic devices of this type belong to the LVC/LCX/Zfamily. In this case, the electronic component is mounted in the way of Surface Mount. This board is designed with 6pins on it. The clock edge trigger type for this device is Positive Edge. The part is included in FF/Latches. Flip flops designed with 1bits are used in this part. Vsup reaches its maximum value at 5.5V. Its superior flexibility is attributed to its use of 1 circuits. As a result of its reliability, this D flip flop is ideally suited for TR. The power supply is 3.3V. This T flip flop features a maximum design flexibility due to its output current of 32mA. Quiescent current is consumed by the D latch in the amount of 10μA.
SN74LVC1G175DBVR Features
Tape & Reel (TR) package
74LVC series
6 pins
1 Bits
3.3V power supplies
SN74LVC1G175DBVR Applications
There are a lot of Texas Instruments SN74LVC1G175DBVR Flip Flops applications.
- Storage registers
- ESCC
- Memory
- Pattern generators
- Patented noise
- Frequency division
- Set-reset capability
- Communications
- Common Clocks
- Buffer registers
