SN74LVC2G74DCURE4
| Parameters | |
|---|---|
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Base Part Number | 74LVC2G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 140MHz |
| Propagation Delay | 6.2 ns |
| Turn On Delay Time | 4.1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, D-Type |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 32mA |
| Number of Gates | 2 |
| Max Propagation Delay @ V, Max CL | 5.1ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 5.9 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Clock Edge Trigger Type | Positive Edge |
| Height | 900μm |
| Length | 2.3mm |
| Width | 2mm |
| Thickness | 850μm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-VFSOP (0.091, 2.30mm Width) |
| Number of Pins | 8 |
| Weight | 9.610488mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
SN74LVC2G74DCURE4 Overview
The package is in the form of 8-VFSOP (0.091, 2.30mm Width). The package Tape & Reel (TR)contains it. In the configuration, Differentialis used as the output. The trigger configured with it uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1.65V~5.5V volts. The operating temperature is -40°C~125°C TA. A flip flop of this type is classified as a D-Type. In FPGA terms, D flip flop is a type of 74LVCseries FPGA. There should be no greater frequency than 140MHzon its output. As a result, it consumes 10μA quiescent current. 8terminations have occurred. This D latch belongs to the family of 74LVC2G74. The power supply voltage is 1.8V. The input capacitance of this T flip flop is 5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It belongs to the family of electronic devices known as LVC/LCX/Z. This electronic part is mounted in the way of Surface Mount. The 8pins are designed into the board. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. It is included in FF/Latches. An electronic part with 1bits has been designed. There is a 5.5Vmaximum supply voltage (Vsup). The superior flexibility of this circuit is achieved by using 1 circuits. As a result of its reliable performance, this T flip flop is suitable for TR. It operates from 3.3V power supplies. The building block contains a total of 2 gates.
SN74LVC2G74DCURE4 Features
Tape & Reel (TR) package
74LVC series
8 pins
1 Bits
3.3V power supplies
2 gates
SN74LVC2G74DCURE4 Applications
There are a lot of Texas Instruments SN74LVC2G74DCURE4 Flip Flops applications.
- High Performance Logic for test systems
- Differential Individual
- Shift Registers
- Bus hold
- Latch-up performance
- Pattern generators
- Storage Registers
- Matched Rise and Fall
- Divide a clock signal by 2 or 4
- Consumer
