SN74LVC374ARGYR
| Parameters | |
|---|---|
| Max I(ol) | 0.024 A |
| Max Propagation Delay @ V, Max CL | 7ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 7 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Number of Input Lines | 3 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1mm |
| Length | 4.5mm |
| Width | 3.5mm |
| Thickness | 900μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 6 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-VFQFN Exposed Pad |
| Number of Pins | 20 |
| Weight | 43.006227mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 20 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVC374 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Number of Circuits | 8 |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Output Current | 24mA |
| Number of Bits | 8 |
| Clock Frequency | 100MHz |
| Propagation Delay | 8.1 ns |
| Turn On Delay Time | 1.5 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
SN74LVC374ARGYR Overview
20-VFQFN Exposed Padis the way it is packaged. Package Cut Tape (CT)embeds it. T flip flop uses Tri-State, Non-Invertedas the output. This trigger uses the value Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. It operates with a supply voltage of 1.65V~3.6V. Temperature is set to -40°C~85°C TA. A flip flop of this type is classified as a D-Type. JK flip flop is a part of the 74LVCseries of FPGAs. It should not exceed 100MHzin its output frequency. In total, it contains 1 elements. T flip flop consumes 10μA quiescent energy. The number of terminations is 20. The 74LVC374family includes it. It is powered by a voltage of 1.8V . Input capacitance of this device is 4pF farads. It is a member of the LVC/LCX/Zfamily of D flip flop. There is an electronic component mounted in the way of Surface Mount. It is designed with 20 pins. The clock edge trigger type for this device is Positive Edge. The part you are looking for is included in FF/Latches. Flip flops designed with 8bits are used in this part. Its flexibility is enhanced by 8 circuits. In light of its reliable performance, this T flip flop is well suited for TR. This D flip flop is equipped with 0 ports. Its output current of 24mAallows for maximum design flexibility. Currently, there are 3 lines of input.
SN74LVC374ARGYR Features
Cut Tape (CT) package
74LVC series
20 pins
8 Bits
SN74LVC374ARGYR Applications
There are a lot of Texas Instruments SN74LVC374ARGYR Flip Flops applications.
- Data Synchronizers
- Balanced 24 mA output drivers
- Latch-up performance
- High Performance Logic for test systems
- Guaranteed simultaneous switching noise level
- Instrumentation
- CMOS Process
- ATE
- Functionally equivalent to the MC10/100EL29
- Bus hold
