SN74LVC74ADE4
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 14 |
| Weight | 129.387224mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latch |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVC74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 100MHz |
| Propagation Delay | 6 ns |
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1.75mm |
| Length | 8.65mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVC74ADE4 Overview
The flip flop is packaged in a case of 14-SOIC (0.154, 3.90mm Width). The Tubepackage contains it. This output is configured with Differential. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Surface Mount. A voltage of 1.65V~3.6Vis used as the supply voltage. A temperature of -40°C~125°C TAis used in the operation. This D latch has the type D-Type. JK flip flop is a part of the 74LVCseries of FPGAs. Its output frequency should not exceed 100MHz Hz. There is 10μA quiescent consumption. A total of 14 terminations have been made. The 74LVC74 family contains this object. A voltage of 1.8V is used to power it. This JK flip flop has a 5pFfarad input capacitance. The electronic device belongs to the LVC/LCX/Zfamily. In this case, the electronic component is mounted in the way of Surface Mount. There are 14pins on it. It has a clock edge trigger type of Positive Edge. The part you are looking for is included in FF/Latch. Vsup reaches its maximum value at 3.6V. Despite its superior flexibility, it relies on 2 circuits to achieve it. The power supply is 3.3V. The 24mA output current allows it to be designed with the greatest amount of flexibility. There are no output lines on the JK flip flop.
SN74LVC74ADE4 Features
Tube package
74LVC series
14 pins
3.3V power supplies
SN74LVC74ADE4 Applications
There are a lot of Texas Instruments SN74LVC74ADE4 Flip Flops applications.
- Load Control
- Latch
- ESD performance
- Dynamic threshold performance
- CMOS Process
- Parallel data storage
- Latch-up performance
- Single Up Count-Control Line
- Storage registers
- Frequency Divider circuits
