SN74LVC74ADG4
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 14 |
| Weight | 129.387224mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Base Part Number | 74LVC74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 100MHz |
| Propagation Delay | 6 ns |
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1.58mm |
| Length | 8.65mm |
| Width | 3.91mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVC74ADG4 Overview
The item is packaged in 14-SOIC (0.154, 3.90mm Width)cases. The Tubepackage contains it. T flip flop is configured with an output of Differential. JK flip flop uses Positive Edgeas the trigger. Surface Mountis positioned in the way of this electronic part. A voltage of 1.65V~3.6Vis required for its operation. It is operating at a temperature of -40°C~125°C TA. This logic flip flop is classified as type D-Type. JK flip flop is a part of the 74LVCseries of FPGAs. A frequency of 100MHzshould not be exceeded by its output. There is 10μA quiescent consumption. There are 14 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. JK flip flop belongs to 74LVC74 family. The power supply voltage is 1.8V. A JK flip flop with a 5pFfarad input capacitance is used here. Devices in the LVC/LCX/Zfamily are electronic devices. There is an electronic component mounted in the way of Surface Mount. It is designed with 14 pins. Its clock edge trigger type is Positive Edge. The part is included in FF/Latches. The maximal supply voltage (Vsup) reaches 3.6V. To achieve this superior flexibility, 2 circuits are used. An electrical current of 3.3V volts is applied to it. It offers maximum design flexibility with its output current of 24mA. It has 1 output lines to operate.
SN74LVC74ADG4 Features
Tube package
74LVC series
14 pins
3.3V power supplies
SN74LVC74ADG4 Applications
There are a lot of Texas Instruments SN74LVC74ADG4 Flip Flops applications.
- Matched Rise and Fall
- Clock pulse
- Power down protection
- ATE
- Consumer
- Frequency division
- Instrumentation
- Digital electronics systems
- Memory
- Shift Registers
