SN74LVC821APWR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 24-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 24 |
| Weight | 89.499445mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74LVC821 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Number of Circuits | 8 |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Output Current | 24mA |
| Clock Frequency | 150MHz |
| Propagation Delay | 8.8 ns |
| Quiescent Current | 10μA |
| Turn On Delay Time | 2.2 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 7.3ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Output Lines | 3 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Height | 1.2mm |
| Length | 7.8mm |
| Width | 4.4mm |
| Thickness | 1mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVC821APWR Overview
The flip flop is packaged in a case of 24-TSSOP (0.173, 4.40mm Width). It is included in the package Cut Tape (CT). T flip flop is configured with an output of Tri-State, Non-Inverted. It is configured with a trigger that uses Positive Edge. It is mounted in the way of Surface Mount. A supply voltage of 1.65V~3.6V is required for operation. It is operating at a temperature of -40°C~85°C TA. It belongs to the type D-Typeof flip flops. JK flip flop is a part of the 74LVCseries of FPGAs. In order for it to function properly, its output frequency should not exceed 150MHz. There are 1 elements in it. A total of 24 terminations have been made. The object belongs to the 74LVC821 family. The power source is powered by 1.8V. A 5pFfarad input capacitance is provided by this T flip flop. It is a member of the LVC/LCX/Zfamily of D flip flop. A part of the electronic system is mounted in the way of Surface Mount. Basically, it is designed with a set of 24 pins. This device exhibits a clock edge trigger type of Positive Edge. This RS flip flops is a part number FF/Latches. Despite its superior flexibility, it relies on 8 circuits to achieve it. A reliable performance of this D flip flop makes it well suited for use in TR. A D flip flop with 2embedded ports is available. In addition to its maximum design flexibility, the output current of the T flip flop is 24mA. There are no output lines on the JK flip flop. In terms of quiescent current, it consumes 10μA .
SN74LVC821APWR Features
Cut Tape (CT) package
74LVC series
24 pins
SN74LVC821APWR Applications
There are a lot of Texas Instruments SN74LVC821APWR Flip Flops applications.
- Divide a clock signal by 2 or 4
- EMI reduction circuitry
- Individual Asynchronous Resets
- Circuit Design
- Cold spare funcion
- Shift Registers
- Single Up Count-Control Line
- ESCC
- Patented noise
- Power down protection
