SN74LVCH16374ADGGR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 48-TFSOP (0.240, 6.10mm Width) |
| Number of Pins | 48 |
| Weight | 223.195796mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74LVCH |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 48 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Base Part Number | 74LVCH16374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 1.65V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Output Current | 24mA |
| Number of Bits | 16 |
| Clock Frequency | 150MHz |
| Propagation Delay | 6.1 ns |
| Quiescent Current | 20μA |
| Turn On Delay Time | 1.5 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 8 |
| Number of Output Lines | 3 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Max Frequency@Nom-Sup | 150000000Hz |
| Height | 1.2mm |
| Length | 12.5mm |
| Width | 6.1mm |
| Thickness | 1.15mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVCH16374ADGGR Overview
48-TFSOP (0.240, 6.10mm Width)is the packaging method. As part of the package Cut Tape (CT), it is embedded. Currently, the output is configured to use Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. The electronic part is mounted in the way of Surface Mount. A voltage of 1.65V~3.6Vis required for its operation. A temperature of -40°C~125°C TAis used in the operation. D-Typedescribes this flip flop. This type of FPGA is a part of the 74LVCH series. It should not exceed 150MHzin its output frequency. A total of 2 elements are present. It has been determined that there have been 48 terminations. JK flip flop belongs to 74LVCH16374 family. The power supply voltage is 1.8V. This JK flip flop has a 5pFfarad input capacitance. In this case, the D flip flop belongs to the LVC/LCX/Zfamily. This electronic part is mounted in the way of Surface Mount. It is designed with 48 pins. In this device, the clock edge trigger type is Positive Edge. The part you are looking for is included in FF/Latches. An electronic part designed with 16bits is used in this application. The supply voltage (Vsup) should be maintained above 1.65V for normal operation. As a result of its reliable performance, this T flip flop is suitable for TR. There are 2 ports embedded in the flip flops. The output current of 24mA makes it feature maximum design flexibility. There are 3 output lines on it. This input has 8lines in it. In terms of quiescent current, it consumes 20μA .
SN74LVCH16374ADGGR Features
Cut Tape (CT) package
74LVCH series
48 pins
16 Bits
SN74LVCH16374ADGGR Applications
There are a lot of Texas Instruments SN74LVCH16374ADGGR Flip Flops applications.
- Convert a momentary switch to a toggle switch
- Bus hold
- Latch-up performance
- Divide a clock signal by 2 or 4
- Memory
- Count Modes
- ATE
- Bounce elimination switch
- Memory
- Asynchronous counter
